PIC18F87J10 Datasheet, PDF (237/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

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19.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTAx<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be used
to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate, depending on the BRGH
and BRG16 bits (TXSTAx<2> and BAUDCONx<3>).
Parity is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
19.2.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 19-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
Once the TXREGx register transfers the data to the TSR
register (occurs in one TCY), the TXREGx register is
empty and the TX1IF flag bit (PIR1<4>) is set. This inter-
rupt can be enabled or disabled by setting or clearing the
interrupt enable bit, TX1IE (PIE1<4>). TX1IF will be set
regardless of the state of TX1IE; it cannot be cleared in
software. TX1IF is also not cleared immediately upon
loading TXREGx, but becomes valid in the second
instruction cycle following the load instruction. Polling
TX1IF immediately following a load of TXREGx will return
invalid results.
While TX1IF indicates the status of the TXREGx regis-
ter, another bit, TRMT (TXSTAx<1>), shows the status
of the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TX1IF is set when enable bit
TXEN is set.
To set up an Asynchronous Transmission:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXxIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN
which will also set bit TXxIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREGx register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-3:
EUSART TRANSMIT BLOCK DIAGRAM
TXxIF
TXxIE
MSb
(8)
Interrupt
TXEN Baud Rate CLK
BRG16
SPBRGHx SPBRGx
Baud Rate Generator
Data Bus
TXREGx Register
8
•••
TSR Register
TX9
TX9D
LSb
0
Pin Buffer
and Control
TRMT
SPEN
TXx pin
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 235