PIC18F87J10 Datasheet, PDF (387/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
Special Function Registers ................................................ 68
Map ............................................................................ 68
SPI Mode (MSSP)
Associated Registers ............................................... 192
Bus Mode Compatibility ........................................... 191
Clock Speed and Module Interactions ..................... 191
Effects of a Reset ..................................................... 191
Enabling SPI I/O ...................................................... 187
Master Mode ............................................................ 188
Master/Slave Connection ......................................... 187
Operation ................................................................. 186
Operation in Power-Managed Modes ...................... 191
Serial Clock .............................................................. 183
Serial Data In ........................................................... 183
Serial Data Out ........................................................ 183
Slave Mode .............................................................. 189
Slave Select ............................................................. 183
Slave Select Synchronization .................................. 189
SPI Clock ................................................................. 188
Typical Connection .................................................. 187
SSP
TMR4 Output for Clock Shift .................................... 158
SSPOV ............................................................................. 214
SSPOV Status Flag ......................................................... 214
SSPSTAT Register
R/W Bit ..................................................................... 198
SSPxSTAT Register
R/W Bit ..................................................................... 197
SSx .................................................................................. 183
Stack Full/Underflow Resets .............................................. 61
SUBFSR .......................................................................... 325
SUBFWB .......................................................................... 314
SUBLW ............................................................................ 315
SUBULNK ........................................................................ 325
SUBWF ............................................................................ 315
SUBWFB .......................................................................... 316
SWAPF ............................................................................ 316
T
Table Pointer Operations (table) ........................................ 82
Table Reads/Table Writes ................................................. 61
TBLRD ............................................................................. 317
TBLWT ............................................................................. 318
Timer0 .............................................................................. 141
Associated Registers ............................................... 143
Operation ................................................................. 142
Overflow Interrupt .................................................... 143
Prescaler .................................................................. 143
Prescaler Assignment (PSA Bit) .............................. 143
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 143
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 142
Source Edge Select (T0SE Bit) ................................ 142
Source Select (T0CS Bit) ......................................... 142
Switching Prescaler Assignment .............................. 143
Timer1 .............................................................................. 145
16-Bit Read/Write Mode ........................................... 147
Associated Registers ............................................... 149
Interrupt .................................................................... 148
Low-Power Option ................................................... 147
Operation ................................................................. 146
Oscillator .......................................................... 145, 147
Layout Considerations ..................................... 148
Oscillator, as Secondary Clock .................................. 30
Overflow Interrupt .................................................... 145
Resetting, Using the CCP
Special Event Trigger ...................................... 148
Special Event Trigger (ECCP) ................................. 170
TMR1H Register ...................................................... 145
TMR1L Register ...................................................... 145
Use as a Clock Source ............................................ 147
Use as a Real-Time Clock ....................................... 148
Timer2 ............................................................................. 151
Associated Registers ............................................... 152
Interrupt ................................................................... 152
Operation ................................................................. 151
Output ...................................................................... 152
PR2 Register ................................................... 164, 171
TMR2 to PR2 Match Interrupt .......................... 164, 171
Timer3 ............................................................................. 153
16-Bit Read/Write Mode .......................................... 155
Associated Registers ............................................... 155
Operation ................................................................. 154
Oscillator .......................................................... 153, 155
Overflow Interrupt ............................................ 153, 155
Special Event Trigger (ECCP) ................................. 155
TMR3H Register ...................................................... 153
TMR3L Register ...................................................... 153
Timer4 ............................................................................. 157
Associated Registers ............................................... 158
Operation ................................................................. 157
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 157
Prescaler. See Prescaler, Timer4.
SSP Clock Shift ....................................................... 158
TMR4 Register ........................................................ 157
TMR4 to PR4 Match Interrupt .......................... 157, 158
Timing Diagrams
A/D Conversion ....................................................... 368
Acknowledge Sequence .......................................... 217
Asynchronous Reception ......................................... 238
Asynchronous Transmission ................................... 236
Asynchronous Transmission
(Back to Back) ................................................. 236
Automatic Baud Rate Calculation ............................ 234
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 239
Auto-Wake-up Bit (WUE) During Sleep ................... 239
Baud Rate Generator with Clock Arbitration ............ 211
BRG Overflow Sequence ........................................ 234
BRG Reset Due to SDAx Arbitration
During Start Condition ..................................... 220
Brown-out Reset (BOR) ........................................... 356
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 221
Bus Collision During a Repeated
Start Condition (Case 2) .................................. 221
Bus Collision During a Start Condition
(SCLx = 0) ....................................................... 220
Bus Collision During a Stop Condition
(Case 1) ........................................................... 222
Bus Collision During a Stop Condition
(Case 2) ........................................................... 222
Bus Collision During Start Condition
(SDAx Only) ..................................................... 219
Bus Collision for Transmit and
Acknowledge ................................................... 218
Capture/Compare/PWM (Including
ECCP Modules) ............................................... 358
CLKO and I/O .......................................................... 353
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 385