PIC18F87J10 Datasheet, PDF (130/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 10-11: PORTE FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/AD8/RD/
RE0
0
O
DIG LATE<0> data output.
P2D
1
I
ST PORTE<0> data input.
AD8⁽³⁾
x
O
DIG External memory interface, address/data bit 8 output.⁽²⁾
x
I
TTL External memory interface, data bit 8 input.⁽²⁾
RD
1
I
TTL Parallel Slave Port read enable control input.
P2D
0
O
DIG ECCP2 Enhanced PWM output, channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1/AD9/WR/
RE1
0
O
DIG LATE<1> data output.
P2C
1
I
ST PORTE<1> data input.
AD9⁽³⁾
x
O
DIG External memory interface, address/data bit 9 output.⁽²⁾
x
I
TTL External memory interface, data bit 9 input.⁽²⁾
WR
1
I
TTL Parallel Slave Port write enable control input.
P2C
0
O
DIG ECCP2 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2/AD10/CS/
RE2
0
P2B
1
AD10⁽³⁾
x
x
O
DIG LATE<2> data output.
I
ST PORTE<2> data input.
O
DIG External memory interface, address/data bit 10 output.⁽²⁾
I
TTL External memory interface, data bit 10 input.⁽²⁾
CS
1
I
TTL Parallel Slave Port chip select control input.
P2B
0
O
DIG ECCP2 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3/AD11/
P3C
RE3
0
1
AD11⁽³⁾
x
x
P3C⁽¹⁾
0
O
DIG LATE<3> data output.
I
ST PORTE<3> data input.
O
DIG External memory interface, address/data bit 11 output.⁽²⁾
I
TTL External memory interface, data bit 11 input.⁽²⁾
O
DIG ECCP3 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE4/AD12/
RE4
0
P3B
1
AD12⁽³⁾
x
x
P3B⁽¹⁾
0
O
DIG LATE<4> data output.
I
ST PORTE<4> data input.
O
DIG External memory interface, address/data bit 12 output.⁽²⁾
I
TTL External memory interface, data bit 12 input.⁽²⁾
O
DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE5/AD13/
RE5
0
P1C
1
AD13⁽³⁾
x
x
P1C⁽¹⁾
0
O
DIG LATE<5> data output.
I
ST PORTE<5> data input.
O
DIG External memory interface, address/data bit 13 output.⁽²⁾
I
TTL External memory interface, data bit 13 input.⁽²⁾
O
DIG ECCP1 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
Note 1:
2:
3:
4:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX configuration bit is set (80-pin devices only).
External memory interface I/O takes priority over all other digital and PSP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when CCP2MX configuration bit is cleared (all devices in Microcontroller mode).
DS39663A-page 128
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 2005 Microchip Technology Inc.