PIC18F87J10 Datasheet, PDF (356/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
FIGURE 26-5:
PROGRAM MEMORY READ TIMING DIAGRAM
OSC1
A<19:16>
BA0
AD<15:0>
ALE
CE
Q1
Q2
Q3
Q4
Q1
Address
150
151
164
171
Address
160
155
167
166
168
Data from External
163
162
161
169
171A
OE
165
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
Q2
Address
Address
TABLE 26-10: CLKO AND I/O TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ
Max
Units
150 _{TadV2alL Address Out Valid to ALE ↓}
(address setup time)
0.25 TCY – 10
—
—
ns
151 TalL2adl ALE ↓ to Address Out Invalid
(address hold time)
5
—
—
ns
155 _{TalL2oeL ALE ↓ to OE ↓}
10
0.125 TCY
—
ns
160 _{TadZ2oeL AD high-Z to OE ↓ (bus release to OE)}
0
—
—
ns
161 _{ToeH2adD OE ↑ to AD Driven}
0.125 TCY – 5
—
—
ns
162 _{TadV2oeH LS Data Valid before OE ↑ (data setup time)}
20
—
—
ns
163 _{ToeH2adl OE ↑ to Data In Invalid (data hold time)}
0
—
—
ns
164 TalH2alL ALE Pulse Width
—
TCY
—
ns
165 ToeL2oeH OE Pulse Width
0.5 TCY – 5 0.5 TCY
—
ns
166 TalH2alH ALE ↑ to ALE ↑ (cycle time)
—
0.25 TCY
—
ns
167 Tacc
Address Valid to Data Valid
0.75 TCY – 25
—
—
ns
168 _Toe
OE ↓ to Data Valid
—
0.5 TCY – 25 ns
169 _{TalL2oeH ALE ↓ to OE ↑}
0.625 TCY – 10 — 0.625 TCY + 10 ns
171 TalH2csL Chip Enable Active to ALE ↓
0.25 TCY – 20
—
—
ns
171A TubL2oeH AD Valid to Chip Enable Active
—
—
10
ns
DS39663A-page 354
Advance Information
 2005 Microchip Technology Inc.