PIC18F87J10 Datasheet, PDF (388/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
Clock Synchronization ............................................. 204
Clock/Instruction Cycle .............................................. 62
EUSART Synchronous Receive
(Master/Slave) .................................................. 367
EUSART Synchronous Transmission
(Master/Slave) .................................................. 367
Example SPI Master Mode (CKE = 0) ..................... 359
Example SPI Master Mode (CKE = 1) ..................... 360
Example SPI Slave Mode (CKE = 0) ....................... 361
Example SPI Slave Mode (CKE = 1) ....................... 362
External Clock (All Modes Except PLL) ................... 351
External Memory Bus for Sleep
(Extended Microcontroller Mode) ................. 92, 94
External Memory Bus for TBLRD
(Extended Microcontroller Mode) ................. 92, 94
Fail-Safe Clock Monitor ............................................ 277
First Start Bit Timing ................................................ 212
Full-Bridge PWM Output .......................................... 175
Half-Bridge Output ................................................... 174
I²C Bus Data ............................................................ 363
I²C Bus Start/Stop Bits ............................................. 363
I²C Master Mode (7 or 10-Bit
Transmission) .................................................. 215
I²C Master Mode (7-Bit Reception) .......................... 216
I²C Slave Mode (10-Bit Reception,
SEN = 0) .......................................................... 201
I²C Slave Mode (10-Bit Reception,
SEN = 1) .......................................................... 206
I²C Slave Mode (10-Bit Transmission) ..................... 202
I²C Slave Mode (7-bit Reception, SEN = 0) ............. 199
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 205
I²C Slave Mode (7-Bit Transmission) ....................... 200
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............. 207
I²C Stop Condition Receive or
Transmit Mode ................................................. 217
Master SSP I²C Bus Data ........................................ 365
Master SSP I²C Bus Start/Stop Bits ........................ 365
Parallel Slave Port (PSP) Read ............................... 140
Parallel Slave Port (PSP) Write ............................... 139
Program Memory Read ............................................ 354
Program Memory Write ............................................ 355
PWM Auto-Shutdown (P1RSEN = 0,
Auto-Restart Disabled) ..................................... 180
PWM Auto-Shutdown (P1RSEN = 1,
Auto-Restart Enabled) ..................................... 180
PWM Direction Change ........................................... 177
PWM Direction Change at Near
100% Duty Cycle ............................................. 177
PWM Output ............................................................ 164
Repeated Start Condition ......................................... 213
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST)
and Power-up Timer (PWRT) .......................... 356
Send Break Character Sequence ............................ 240
Slave Synchronization ............................................. 189
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 47
SPI Mode (Master Mode) ......................................... 188
SPI Mode (Slave Mode, CKE = 0) ........................... 190
SPI Mode (Slave Mode, CKE = 1) ........................... 190
Synchronous Reception
(Master Mode, SREN) ...................................... 243
Synchronous Transmission ...................................... 241
Synchronous Transmission
(Through TXEN) ............................................... 242
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ...................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ...................... 47
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise < TPWRT) ........... 46
Timer0 and Timer1 External Clock .......................... 357
Transition for Entry to Idle Mode ................................ 40
Transition for Entry to SEC_RUN Mode .................... 37
Transition for Entry to Sleep Mode ............................ 39
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 275
Transition for Wake from Idle to
Run Mode .......................................................... 40
Transition for Wake from Sleep (HSPLL) .................. 39
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 38
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 37
Transition to RC_RUN Mode ..................................... 38
Timing Diagrams and Specifications
A/D Conversion Requirements ................................ 369
AC Characteristics
Internal RC Accuracy ....................................... 352
Capture/Compare/PWM Requirements
(Including ECCP Modules) .............................. 358
CLKO and I/O Requirements ........................... 353, 354
EUSART Synchronous Receive
Requirements .................................................. 367
EUSART Synchronous Transmission
Requirements .................................................. 367
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 359
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 360
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 361
Example SPI Slave Mode Requirements
(CKE = 1) ......................................................... 362
External Clock Requirements .................................. 351
I²C Bus Data Requirements
(Slave Mode) ................................................... 364
I²C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 363
Master SSP I²C Bus Data Requirements ................ 366
Master SSP I²C Bus Start/Stop Bits
Requirements .................................................. 365
Parallel Slave Port Requirements ............................ 358
PLL Clock ................................................................ 352
Program Memory Write Requirements .................... 355
Reset, Watchdog Timer,
Oscillator Start-up Timer,
Power-up Timer and Brown-out
Reset Requirements ........................................ 356
Timer0 and Timer1 External
Clock Requirements ........................................ 357
Top-of-Stack Access .......................................................... 59
TRISE Register
PSPMODE Bit .......................................................... 138
TSTFSZ ........................................................................... 319
Two-Speed Start-up ................................................. 267, 275
Two-Word Instructions
Example Cases .......................................................... 63
TXSTAx Register
BRGH Bit ................................................................. 229
DS39663A-page 386
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