PIC18F87J10 Datasheet, PDF (162/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
16.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
16.1.1 CCP MODULES AND TIMER
RESOURCES
The CCP/ECCP modules utilize Timers 1, 2, 3 or 4,
depending on the mode selected. Timer1 and Timer3
are available to modules in Capture or Compare
modes, while Timer2 and Timer4 are available for
modules in PWM mode.
TABLE 16-1: CCP MODE – TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 14-1, page 153). Depending
on the configuration selected, up to four timers may be
active at once, with modules in the same configuration
(Capture/Compare or PWM) sharing timer resources.
The possible configurations are shown in Figure 16-1.
16.1.2 ECCP2 PIN ASSIGNMENT
The pin assignment for ECCP2 (Capture input,
Compare and PWM output) can change, based on
device configuration. The CCP2MX configuration bit
determines which pin ECCP2 is multiplexed to. By
default, it is assigned to RC1 (CCP2MX = 1). If the con-
figuration bit is cleared, ECCP2 is multiplexed with RE7
on 64-pin devices and RB3 or RE7 on 80-pin devices
depending on mode setting.
Changing the pin assignment of ECCP2 does not auto-
matically change any requirements for configuring the
port pin. Users must always verify that the appropriate
TRIS register is configured correctly for ECCP2
operation regardless of where it is located.
FIGURE 16-1:
CCP AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP<2:1> = 00
T3CCP<2:1> = 01
T3CCP<2:1> = 10
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
T3CCP<2:1> = 11
TMR1
TMR3
ECCP1
ECCP2
ECCP3
CCP4
CCP5
ECCP1
ECCP2
ECCP3
CCP4
CCP5
ECCP1
ECCP2
ECCP3
CCP4
CCP5
ECCP1
ECCP2
ECCP3
CCP4
CCP5
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
Timer1 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Timer3 and Timer4 are not
available.
Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for ECCP1
only (depending on selected
mode).
All other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base if they are in
Capture/Compare or PWM
modes.
Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for ECCP1
and ECCP2 only (depending
on the mode selected for each
module). Both modules may
use a timer as a common time
base if they are both in
Capture/Compare or PWM
modes.
The other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base if they are in
Capture/Compare or PWM
modes.
Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer4 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Timer1 and Timer2 are not
available.
DS39663A-page 160
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 2005 Microchip Technology Inc.