PIC18F87J10 Datasheet, PDF (286/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 24-2: PIC18F87J10 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
16-Bit Instruction Word
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW k
Add literal and WREG
1
ANDLW k
AND literal with WREG
1
IORLW k
Inclusive OR literal with WREG 1
LFSR
f, k Move literal (12-bit) 2nd word 2
to FSR(f) 1st word
MOVLB k
Move literal to BSR<3:0>
1
MOVLW k
Move literal to WREG
1
MULLW k
Multiply literal with WREG
1
RETLW k
Return with literal in WREG
2
SUBLW k
Subtract WREG from literal
1
XORLW k
Exclusive OR literal with WREG 1
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000 1000 None
TBLRD*+
Table Read with post-increment
0000 0000 0000 1001 None
TBLRD*-
Table Read with post-decrement
0000 0000 0000 1010 None
TBLRD+*
Table Read with pre-increment
0000 0000 0000 1011 None
TBLWT*
Table Write
2
0000 0000 0000 1100 None
5
TBLWT*+
Table Write with post-increment
0000 0000 0000 1101 None
5
TBLWT*-
Table Write with post-decrement
0000 0000 0000 1110 None
5
TBLWT+*
Table Write with pre-increment
0000 0000 0000 1111 None
5
Note 1: When a port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: In normal execution modes, table write operations cannot be used to write to any on-chip memory space. For
80-pin devices, table write instructions may also be used to write to an external memory device. For more
information, see Section 6.4 “Writing to Program Memory Space (PIC18F8XJ10/8XJ15 Devices Only)”
and Section 6.6 “Writing and Erasing On-Chip Program Memory (ICSP Mode)”.
DS39663A-page 284
Advance Information
 2005 Microchip Technology Inc.