PIC18F87J10 Datasheet, PDF (25/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP
Type Type
Description
RG0/ECCP3/P3A
RG0
ECCP3
P3A
PORTG is a bidirectional I/O port.
5
I/O
ST
Digital I/O.
I/O
ST
Capture 3 input/Compare 3 output/PWM 3 output.
O
TTL
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
TX2
CK2
6
I/O
ST
Digital I/O.
O
—
EUSART2 asynchronous transmit.
I/O
ST
EUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
RX2
DT2
7
I/O
ST
Digital I/O.
I
ST
EUSART2 asynchronous receive.
I/O
ST
EUSART2 synchronous data (see related TX2/CK2).
RG3/CCP4/P3D
RG3
CCP4
P3D
8
I/O
ST
Digital I/O.
I/O
ST
Capture 4 input/Compare 4 output/PWM 4 output.
O
TTL
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
CCP5
P1D
10
I/O
ST
Digital I/O.
I/O
ST
Capture 5 input/Compare 5 output/PWM 5 output.
O
TTL
ECCP1 PWM output D.
Legend:
Note 1:
2:
3:
4:
5:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD
= Open-Drain (no P diode to VDD)
Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 23