PIC18F87J10 Datasheet, PDF (240/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
FIGURE 19-7:
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit bit 0 bit 1
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREGx
Start
bit 7/8 Stop bit
bit
Word 2
RCREGx
bit 7/8 Stop
bit
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
49
PIR1
PSPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 51
PIE1
PSPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 51
IPR1
PSPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 51
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 51
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 51
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 51
RCSTAx
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
51
RCREGx EUSARTx Receive Register
51
TXSTAx
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
51
BAUDCONx ABDOVF RCMT
—
SCKP BRG16
—
WUE ABDEN
52
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
52
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
52
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
19.2.4 AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RXx/DTx line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the LIN
protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 19-8) and asynchronously if the device is in
Sleep mode (Figure 19-9). The interrupt condition is
cleared by reading the RCREGx register.
The WUE bit is automatically cleared once a
low-to-high transition is observed on the RXx line
following the wake-up event. At this point, the EUSART
module is in Idle mode and returns to normal operation.
This signals to the user that the Sync Break event is
over.
DS39663A-page 238
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 2005 Microchip Technology Inc.