PIC18F87J10 Datasheet, PDF (135/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 10-15: PORTG FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/ECCP3/
RG0
0
O
DIG LATG<0> data output.
P3A
1
I
ST PORTG<0> data input.
ECCP3
O
DIG CCP3 Compare and PWM output; takes priority over port data.
I
ST CCP3 Capture input.
P3A
0
O
DIG ECCP3 Enhanced PWM output, channel A; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG1/TX2/CK2 R21
0
O
DIG LATG<1> data output.
1
I
ST PORTG<1> data input.
TX2
1
O
DIG Synchronous serial data output (EUSART2 module); takes priority over
port data.
CK2
1
O
DIG Synchronous serial data input (EUSART2 module). User must configure
as an input.
1
I
ST Synchronous serial clock input (EUSART2 module).
RG2/RX2/DT2 RG2
0
O
DIG LATG<2> data output.
1
I
ST PORTG<2> data input.
RX2
1
I
ST Asynchronous serial receive data input (EUSART2 module).
DT2
1
O
DIG Synchronous serial data output (EUSART2 module); takes priority over
port data.
1
I
ST Synchronous serial data input (EUSART2 module). User must configure
as an input.
RG3/CCP4/
RG3
0
O
DIG LATG<3> data output.
P3D
1
I
ST PORTG<3> data input.
CCP4
0
O
DIG CCP4 Compare output and CCP4 PWM output; takes priority over port data.
1
I
ST CCP4 Capture input.
P3D
0
O
DIG ECCP3 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG4/CCP5/
RG4
0
O
DIG LATG<4> data output.
P1D
1
I
ST PORTG<4> data input.
CCP5
0
O
DIG CCP5 Compare output and CCP5 PWM output; takes priority over port data.
1
I
ST CCP5 Capture input.
P1D
0
O
DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTG
RDPU REPU RJPU⁽¹⁾ RG4
RG3
RG2
RG1
LATG
—
—
—
LATG4 LATG3 LATG2 LATG1
TRISG
—
—
— TRISG4 TRISG3 TRISG2 TRISG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on 64-pin devices; read as ‘0’.
Bit 0
Reset
Values on
page
RG0
52
LATG0
52
TRISG0
52
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 133