PIC18F87J10 Datasheet, PDF (22/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP
Type Type
Description
RD0/AD0/PSP0
RD0
AD0
PSP0
PORTD is a bidirectional I/O port.
72
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 0.
I/O TTL
Parallel Slave Port data.
RD1/AD1/PSP1
RD1
AD1
PSP1
69
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 1.
I/O TTL
Parallel Slave Port data.
RD2/AD2/PSP2
RD2
AD2
PSP2
68
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 2.
I/O TTL
Parallel Slave Port data.
RD3/AD3/PSP3
RD3
AD3
PSP3
67
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 3.
I/O TTL
Parallel Slave Port data.
RD4/AD4/PSP4/SDO2
RD4
AD4
PSP4
SDO2
66
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 4.
I/O TTL
Parallel Slave Port data.
O
—
SPI™ data out.
RD5/AD5/PSP5/
SDI2/SDA2
RD5
AD5
PSP5
SDI2
SDA2
65
I/O
ST
I/O TTL
I/O TTL
I
ST
I/O
ST
Digital I/O.
External memory address/data 5.
Parallel Slave Port data.
SPI data in.
I²C™ data I/O.
RD6/AD6/PSP6/
SCK2/SCL2
RD6
AD6
PSP6
SCK2
SCL2
64
I/O
ST
I/O TTL
I/O TTL
I/O
ST
I/O
ST
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I²C mode.
RD7/AD7/PSP7/SS2
RD7
AD7
PSP7
SS2
63
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 7.
I/O TTL
Parallel Slave Port data.
I
TTL
SPI slave select input.
Legend:
Note 1:
2:
3:
4:
5:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD
= Open-Drain (no P diode to VDD)
Alternate assignment for ECCP2/P2A when configuration bit CCP2MX is cleared (Extended Microcontroller mode).
Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
Default assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is set).
Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX configuration bit is cleared).
DS39663A-page 20
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 2005 Microchip Technology Inc.