PIC18F87J10 Datasheet, PDF (72/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 5-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED)
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TMR0H
Timer0 Register High Byte
0000 0000 50, 143
TMR0L
Timer0 Register Low Byte
xxxx xxxx 50, 143
T0CON
OSCCON
TMR0ON
IDLEN
T08BIT
—
T0CS
—
T0SE
—
PSA
OSTS⁽⁵⁾
T0PS2
—
T0PS1
SCS1
T0PS0
SCS0
1111 1111 50, 141
0--- q-00 32, 50
WDTCON
—
—
—
—
—
—
—
SWDTEN --- ---0 50, 273
RCON
IPEN
—
—
RI
TO
PD
POR
BOR 0--1 1100 44, 50,
113
TMR1H
Timer1 Register High Byte
xxxx xxxx 50, 149
TMR1L
Timer1 Register Low Byte
xxxx xxxx 50, 149
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 145
TMR2
Timer2 Register
0000 0000 50, 152
PR2
Timer2 Period Register
1111 1111 50, 152
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 151
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSP1ADD MSSP1 Address Register (I²C™ Slave mode), MSSP1 Baud Rate Reload Register (I²C Master mode)
xxxx xxxx
0000 0000
50, 184,
193
50, 193
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 50, 184,
194
SSP1CON1 WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 50, 185,
195
SSP1CON2 GCEN ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN 0000 0000 50, 196
ADRESH A/D Result Register High Byte
xxxx xxxx 50, 255
ADRESL
A/D Result Register Low Byte
xxxx xxxx 50, 255
ADCON0
ADCAL
—
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON 0-00 0000 50, 247
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0 --00 0000 50, 248
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0-00 0000 50, 249
CCPR1H Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 51, 182
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 51, 182
CCP1CON
P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 51, 167
CCPR2H Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 51, 182
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 51, 182
CCP2CON
P2M1
P2M0
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 51, 167
CCPR3H Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 51, 182
CCPR3L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 51, 182
CCP3CON
ECCP1AS
P3M1
P3M0
DC3B1
DC3B0 CCP3M3
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1
CCP3M2 CCP3M1 CCP3M0 0000 0000 51, 167
PSS1AC0 PSS1BD1⁽²⁾ PSS1BD0⁽²⁾ 0000 0000 51, 179
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0 0000 0000 51, 263
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0 0000 0111 51, 257
TMR3H
Timer3 Register High Byte
xxxx xxxx 51, 155
TMR3L
Timer3 Register Low Byte
xxxx xxxx 51, 155
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 51, 153
PSPCON
IBF
OBF
IBOV PSPMODE
—
—
—
—
0000 ---- 51, 139
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Bit 21 of the PC is only available in Serial Programming modes.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller
mode.
The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
DS39663A-page 70
Advance Information
 2005 Microchip Technology Inc.