PIC18F87J10 Datasheet, PDF (71/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 5-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY)
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 49, 59
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 49, 59
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 49, 59
STKPTR
PCLATU
STKFUL
—
STKUNF
—
—
bit 21⁽¹⁾
Return Stack Pointer
Holding Register for PC<20:16>
00-0 0000 49, 60
---0 0000 49, 59
PCLATH
Holding Register for PC<15:8>
0000 0000 49, 59
PCL
PC Low Byte (PC<7:0>)
0000 0000 49, 59
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 49, 82
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 49, 82
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 49, 82
TABLAT
Program Memory Table Latch
0000 0000 49, 82
PRODH
Product Register High Byte
xxxx xxxx 49, 97
PRODL
Product Register Low Byte
xxxx xxxx 49, 97
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 49, 101
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
RBIP 1111 1111 49, 102
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF 1100 0000 49, 103
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
49, 75
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
49, 76
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
49, 76
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
49, 76
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
49, 76
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx 49, 75
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 49, 75
WREG
Working Register
xxxx xxxx 49
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
49, 75
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
49, 76
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
49, 76
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
49, 76
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
49, 76
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 49, 75
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 49, 75
BSR
—
—
—
—
Bank Select Register
---- 0000 49, 64
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
50, 75
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
50, 76
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
50, 76
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
50, 76
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
50, 76
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 50, 75
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 50, 75
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 50, 73
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Bit 21 of the PC is only available in Serial Programming modes.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller
mode.
The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 69