PIC18F87J10 Datasheet, PDF (73/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 5-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED)
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte
0000 0000 51, 229
RCREG1 EUSART1 Receive Register
0000 0000 51, 237,
238
TXREG1
EUSART1 Transmit Register
xxxx xxxx 51, 235,
236
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 51, 226
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 51, 227
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP 1111 1111 51, 112
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF 0000 0000 51, 106
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE 0000 0000 51, 109
IPR2
OSCFIP
CMIP
—
—
BCL1IP
—
TMR3IP
CCP2IP 11-- 1-11 51, 111
PIR2
OSCFIF
CMIF
—
—
BCL1IF
—
TMR3IF
CCP2IF 00-- 0-00 51, 105
PIE2
OSCFIE
CMIE
—
—
BCL1IE
—
TMR3IE
CCP2IE 00-- 0-00 51, 108
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP 1111 1111 51, 110
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF 0000 0000 51, 104
PIE1
MEMCON⁽³⁾
OSCTUNE
TRISJ⁽²⁾
TRISH⁽²⁾
PSPIE
EBDIS
—
TRISJ7
TRISH7
ADIE
—
PLLEN⁽⁴⁾
TRISJ6
TRISH6
RC1IE
WAIT1
—
TRISJ5
TRISH5
TX1IE
WAIT0
—
TRISJ4
TRISH4
SSP1IE
—
—
TRISJ3
TRISH3
CCP1IE
—
—
TRISJ2
TRISH2
TMR2IE
WM1
—
TRISJ1
TRISH1
TMR1IE
WM0
—
TRISJ0
TRISH0
0000 0000
0-00 --00
-0-- ----
1111 1111
1111 1111
51, 107
51, 86
29, 51
52, 137
52, 135
TRISG
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0 ---1 1111 52, 133
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
1111 111- 52, 131
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0 1111 1111 52, 129
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0 1111 1111 52, 126
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0 1111 1111 52, 123
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0 1111 1111 52, 120
TRISA
LATJ⁽²⁾
LATH⁽²⁾
—
LATJ7
LATH7
—
LATJ6
LATH6
TRISA5
LATJ5
LATH5
TRISA4
LATJ4
LATH4
TRISA3
LATJ3
LATH3
TRISA2
LATJ2
LATH2
TRISA1
LATJ1
LATH1
TRISA0
LATJ0
LATH0
--11 1111
xxxx xxxx
xxxx xxxx
52, 117
52, 137
52, 135
LATG
—
—
—
LATG4
LATG3
LATG2
LATG1
LATG0 ---x xxxx 52, 133
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
—
xxxx xxx- 52, 131
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0 xxxx xxxx 52, 129
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0 xxxx xxxx 52, 126
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 xxxx xxxx 52, 123
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0 xxxx xxxx 52, 120
LATA
PORTJ⁽²⁾
PORTH⁽²⁾
PORTG
—
RJ7
RH7
RDPU
—
RJ6
RH6
REPU
LATA5
RJ5
RH5
RJPU⁽²⁾
LATA4
RJ4
RH4
RG4
LATA3
RJ3
RH3
RG3
LATA2
RJ2
RH2
RG2
LATA1
RJ1
RH1
RG1
LATA0
RJ0
RH0
RG0
--xx xxxx
xxxx xxxx
0000 xxxx
111x xxxx
52, 117
52, 137
52, 135
52, 133
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
x000 000- 52, 131
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx xxxx 52, 129
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0 xxxx xxxx 52, 126
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx 52, 123
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx 52, 120
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000 52, 117
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Bit 21 of the PC is only available in Serial Programming modes.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller
mode.
The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 71