|
PIC18F87J10 Datasheet, PDF (368/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology | |||
|
◁ |
PIC18F87J10 FAMILY
TABLE 26-23: MASTER SSP I2C⢠BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) â ms
400 kHz mode 2(TOSC)(BRG + 1) â ms
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) â ms
400 kHz mode 2(TOSC)(BRG + 1) â ms
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms
102 TR
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
1 MHz mode(1)
â
20 + 0.1 CB
â
1000
300
300
ns CB is specified to be from
ns 10 to 400 pF
ns
103 TF
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
1 MHz mode(1)
â
20 + 0.1 CB
â
300 ns CB is specified to be from
300 ns 10 to 400 pF
100 ns
90
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) â ms Only relevant for
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) â
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms Repeated Start
condition
ms
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) â ms After this period, the first
Hold Time
400 kHz mode 2(TOSC)(BRG + 1) â
ms clock pulse is generated
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms
106 THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
0
0
TBD
â
ns
0.9 ms
â
ns
107 TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
250
100
TBD
â
ns (Note 2)
â
ns
â
ns
92
TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) â ms
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) â ms
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms
109 TAA
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
â
3500 ns
â
1000 ns
â
â
ns
110 TBUF Bus Free Time 100 kHz mode
400 kHz mode
1 MHz mode(1)
4.7
1.3
TBD
â ms Time the bus must be free
â
ms before a new transmission
can start
â ms
D102 CB
Bus Capacitive Loading
â
400 pF
Legend:
Note 1:
2:
TBD = To Be Determined
Maximum pin capacitance = 10 pF for all I2C⢠pins.
A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ⥠250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data
bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before
the SCLx line is released.
DS39663A-page 366
Advance Information
 2005 Microchip Technology Inc.
|
▷ |