PIC18F87J10 Datasheet, PDF (85/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
READ_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
TBLRD*+
MOVF TABLAT, W
MOVWF WORD_EVEN
TBLRD*+
MOVFW TABLAT, W
MOVF WORD_ODD
; Load TBLPTR with the base
; address of the word
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
6.4 Writing to Program Memory Space
(PIC18F8XJ10/8XJ15 Devices
Only)
The table write operation outputs the contents of the
TBLPTR and TABLAT registers to the external address
and data busses of the external memory interface.
Depending on the program memory mode selected, the
operation may target any byte address in the device’s
memory space. What happens to this data depends
largely on the external memory device being used.
For PIC18 devices with Enhanced Flash memory, a
single algorithm is used for writing to the on-chip pro-
gram array. In the case of external devices, however,
the algorithm is determined by the type of memory
device and its requirements. In some cases, a specific
instruction sequence must be sent before data can be
written or erased. Address and data demultiplexing,
chip select operation and write time requirements must
all be considered in creating the appropriate code.
The connection of the data and address busses to the
memory device are dictated by the interface being
used, the data bus width and the target device. When
using a 16-bit data path, the algorithm must take into
account the width of the target memory.
Another important consideration is the write time
requirement of the target device. If this is longer than
the time that a TBLWT operation makes data available
on the interface, the algorithm must be adjusted to
lengthen this time. It may be possible, for example, to
buy enough time by increasing the length of the wait
state on table operations.
In all cases, it is important to remember that instruc-
tions in the program memory space are word-aligned,
with the Least Significant bit always being written to an
even-numbered address (LSb = 0). If data is being
stored in the program memory space, word alignment
of the data is not required.
A complete overview of interface algorithms is beyond
the scope of this data sheet. The best place for timing
and instruction sequence requirements is the data
sheet of the memory device in question. For additional
information algorithm design for the external memory
interface, refer to Microchip application note AN869,
“External Memory Interfacing Techniques for the
PIC18F8XXX” (DS00869).
6.4.1 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.4.2
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the application writes to external
memory on a frequent basis, it may be necessary to
implement an error trapping routine to handle these
unplanned events.
6.5 Erasing External Memory
(PIC18F8XJ10/8XJ15 Devices
Only)
Erasure is implemented in different ways on different
devices. In many cases, it is possible to erase all or part
of the memory by issuing a specific command. In some
devices, it may be necessary to write ‘0’s to the
locations to be erased. For specific information, consult
the data sheet for the memory device in question.
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 83