PIC18F87J10 Datasheet, PDF (380/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
BOV .................................................................................. 293
BRA .................................................................................. 291
Break Character (12-Bit) Transmit
and Receive ............................................................. 240
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..................................................... 45
and On-Chip Voltage Regulator ............................... 274
Disabling in Sleep Mode ............................................ 45
BSF .................................................................................. 291
BSR .................................................................................... 79
BTFSC ............................................................................. 292
BTFSS .............................................................................. 292
BTG .................................................................................. 293
BZ ..................................................................................... 294
C
C Compilers
MPLAB C17 ............................................................. 330
MPLAB C18 ............................................................. 330
MPLAB C30 ............................................................. 330
Calibration (A/D Converter) .............................................. 255
CALL ................................................................................ 294
CALLW ............................................................................. 323
Capture (CCP Module) ..................................................... 161
Associated Registers ............................................... 163
CCP Pin Configuration ............................................. 161
CCPRxH:CCPRxL Registers ................................... 161
Prescaler .................................................................. 161
Software Interrupt .................................................... 161
Timer1/Timer3 Mode Selection ................................ 161
Capture (ECCP Module) .................................................. 170
Capture/Compare/PWM (CCP) ........................................ 159
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 160
CCPRxH Register .................................................... 160
CCPRxL Register ..................................................... 160
Compare Mode. See Compare.
Interconnect Configurations ..................................... 160
Module Configuration ............................................... 160
Clock Sources .................................................................... 30
Default System Clock on Reset ................................. 31
Selection Using OSCCON Register ........................... 31
Clocking Scheme/Instruction Cycle .................................... 62
CLRF ................................................................................ 295
CLRWDT .......................................................................... 295
Code Examples
16 x 16 Signed Multiply Routine ................................ 98
16 x 16 Unsigned Multiply Routine ............................ 98
8 x 8 Signed Multiply Routine .................................... 97
8 x 8 Unsigned Multiply Routine ................................ 97
Changing Between Capture Prescalers ................... 161
Computed GOTO Using an Offset Value ................... 61
Fast Register Stack .................................................... 61
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................ 74
Implementing a Real-Time Clock
Using a Timer1 Interrupt Service ..................... 149
Initializing PORTA .................................................... 116
Initializing PORTB .................................................... 118
Initializing PORTC .................................................... 121
Initializing PORTD .................................................... 124
Initializing PORTE .................................................... 127
Initializing PORTF .................................................... 130
Initializing PORTG ................................................... 132
Initializing PORTH .................................................... 134
Initializing PORTJ .................................................... 136
Loading the SSP1BUF
(SSP1SR) Register .......................................... 186
Reading a Flash Program Memory Word .................. 83
Saving STATUS, WREG and
BSR Registers in RAM .................................... 114
Code Protection ............................................................... 267
COMF .............................................................................. 296
Comparator ...................................................................... 257
Analog Input Connection Considerations ................ 261
Associated Registers ............................................... 261
Configuration ........................................................... 258
Effects of a Reset .................................................... 260
Interrupts ................................................................. 260
Operation ................................................................. 259
Operation During Sleep ........................................... 260
Outputs .................................................................... 259
Reference ................................................................ 259
External Signal ................................................ 259
Internal Signal .................................................. 259
Response Time ........................................................ 259
Comparator Specifications ............................................... 348
Comparator Voltage Reference ....................................... 263
Accuracy and Error .................................................. 264
Associated Registers ............................................... 265
Configuring .............................................................. 263
Connection Considerations ...................................... 264
Effects of a Reset .................................................... 264
Operation During Sleep ........................................... 264
Compare (CCP Module) .................................................. 162
Associated Registers ............................................... 163
CCPRx Register ...................................................... 162
Pin Configuration ..................................................... 162
Software Interrupt .................................................... 162
Timer1/Timer3 Mode Selection ................................ 162
Compare (ECCP Module) ................................................ 170
Special Event Trigger .............................. 155, 170, 254
Computed GOTO ............................................................... 61
Configuration Bits ............................................................ 267
Configuration Register Protection .................................... 278
Context Saving During Interrupts ..................................... 114
CPFSEQ .......................................................................... 296
CPFSGT .......................................................................... 297
CPFSLT ........................................................................... 297
Crystal Oscillator/Ceramic Resonator ................................ 27
Customer Change Notification Service ............................ 387
Customer Notification Service ......................................... 387
Customer Support ............................................................ 387
D
Data Addressing Modes .................................................... 74
Comparing Addressing Modes with the
Extended Instruction Set Enabled ..................... 78
Direct ......................................................................... 74
Indexed Literal Offset ................................................ 77
Indirect ....................................................................... 74
Inherent and Literal .................................................... 74
Data Memory ..................................................................... 64
Access Bank .............................................................. 67
and the Extended Instruction Set .............................. 77
Bank Select Register (BSR) ...................................... 64
General Purpose Registers ....................................... 67
Map for PIC18FX5J10/X5J15/X6J10 Devices ........... 65
Map for PIC18FX6J15/X7J10 Devices ...................... 66
Special Function Registers ........................................ 68
DAW ................................................................................ 298
DS39663A-page 378
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