PIC18F87J10 Datasheet, PDF (247/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
49
PIR1
PSPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
51
PIE1
PSPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
51
IPR1
PSPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
51
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 51
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 51
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 51
RCSTAx
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
51
TXREGx EUSARTx Transmit Register
51
TXSTAx
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
51
BAUDCONx ABDOVF RCMT
—
SCKP BRG16
—
WUE ABDEN
52
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
52
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
19.4.2 EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register; if the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCxIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
6. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 245