PIC18F87J10 Datasheet, PDF (225/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
TABLE 18-4: REGISTERS ASSOCIATED WITH I²C™ OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
49
PIR1
PSPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
51
PIE1
PSPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
51
IPR1
PSPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
51
PIR2
OSCFIF CMIF
—
—
BCL1IF
—
TMR3IF CCP2IF 51
PIE2
OSCFIE CMIE
—
—
BCL1IE
—
TMR3IE CCP2IE 51
IPR2
OSCFIP CMIP
—
—
BCL1IP
—
TMR3IP CCP2IP 51
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 51
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 51
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 51
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 52
TRISD
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 52
SSP1BUF MSSP1 Receive Buffer/Transmit Register
50
SSP1ADD MSSP1 Address Register (I²C™ Slave mode),
53
MSSP1 Baud Rate Reload Register (I²C Master mode)
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
50
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN
PEN
RSEN
SEN
50
SSP1STAT SMP
CKE
D/A
P
S
R/W
UA
BF
50
SSP2BUF MSSP2 Receive Buffer/Transmit Register
50
SSP2ADD MSSP2 Address Register (I²C Slave mode),
53
MSSP2 Baud Rate Reload Register (I²C Master mode)
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
53
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN
PEN
RSEN
SEN
53
SSP2STAT SMP
CKE
D/A
P
S
R/W
UA
BF
53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I²C™ mode.
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 223