PIC18F87J90 Datasheet, PDF (79/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
TABLE 6-3: PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page
PORTJ⁽²⁾
PORTH⁽²⁾
PORTG
RJ7
RH7
RDPU
RJ6
RH6
REPU
RJ5
RH5
RJPU⁽²⁾
RJ4
RH4
RG4
RJ3
RH3
RG3
RJ2
RH2
RG2
RJ1
RH1
RG1
RJ0
RH0
RG0
xxxx xxxx
xxxx xxxx
000x xxxx
62, 138
62, 136
62, 134
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
xxxx xxx- 62, 132
PORTE
RE7
RE6
RE5
RE4
RE3
—
RE1
RE0 xxxx x-xx 63, 129
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0 xxxx xxxx 63, 127
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx 63, 125
PORTB
PORTA
RB7
RA7⁽⁵⁾
RB6
RA6⁽⁵⁾
RB5
RA5
RB4
RA4
RB3
RA3
RB2
RA2
RB1
RA1
RB0 xxxx xxxx 63, 122
RA0 xx0x 0000 63, 119
SPBRGH1
EUSART Baud Rate Generator High Byte
0000 0000 63, 259
BAUDCON1
LCDDATA23⁽²⁾
LCDDATA22
ABDOVF
S47C3
S39C3⁽²⁾
RCIDL
S46C3
S38C3⁽²⁾
RXDTP
S45C3
S37C3⁽²⁾
TXCKP
S44C3
S36C3⁽²⁾
BRG16
S43C3
S35C3⁽²⁾
—
S42C3
S34C3⁽²⁾
WUE
S41C3
S33C3⁽²⁾
ABDEN
S40C3
S32C3
0100 0-00
xxxx xxxx
xxxx xxxx
63, 258
63, 187
63, 187
LCDDATA21
S31C3
S30C3
S29C3
S28C3
S27C3
S26C3
S25C3
S24C3 xxxx xxxx 63, 187
LCDDATA20
S23C3
S22C3
S21C3
S20C3
S19C3
S18C3
S17C3
S16C3 xxxx xxxx 63, 187
LCDDATA19
S15C3
S14C3
S13C3
S12C3
S11C3
S10C3
S09C3
S08C3 xxxx xxxx 63, 187
LCDDATA18
LCDDATA17⁽²⁾
LCDDATA16
S07C3
S47C2
S39C2⁽²⁾
S06C3
S46C2
S38C2⁽²⁾
S05C3
S45C2
S37C2⁽²⁾
S04C3
S44C2
S36C2⁽²⁾
S03C3
S43C2
S35C2⁽²⁾
S02C3
S42C2
S34C2⁽²⁾
S01C3
S41C2
S33C2⁽²⁾
S00C3
S40C2
S32C2
xxxx xxxx
xxxx xxxx
xxxx xxxx
63, 187
63, 187
63, 187
LCDDATA15
S31C2
S30C2
S29C2
S28C2
S27C2
S26C2
S25C2
S24C2 xxxx xxxx 63, 187
LCDDATA14
S23C2
S22C2
S21C2
S20C2
S19C2
S18C2
S17C2
S16C2 xxxx xxxx 63, 187
LCDDATA13
S15C2
S14C2
S13C2
S12C2
S11C2
S10C2
S09C2
S08C2 xxxx xxxx 63, 187
LCDDATA12
LCDDATA11⁽²⁾
LCDDATA10
S07C2
S47C1
S39C1⁽²⁾
S06C2
S46C1
S38C1⁽²⁾
S05C2
S45C1
S37C1⁽²⁾
S04C2
S44C1
S36C1⁽²⁾
S03C2
S43C1
S35C1⁽²⁾
S02C2
S42C1
S34C1⁽²⁾
S01C2
S41C1
S33C1⁽²⁾
S00C2
S40C1
S32C1
xxxx xxxx
xxxx xxxx
xxxx xxxx
63, 187
63, 187
63, 187
LCDDATA9
S31C1
S30C1
S29C1
S28C1
S27C1
S26C1
S25C1
S24C1 xxxx xxxx 63, 187
LCDDATA8
S23C1
S22C1
S21C1
S20C1
S19C1
S18C1
S17C1
S16C1 xxxx xxxx 63, 187
LCDDATA7
S15C1
S14C1
S13C1
S12C1
S11C1
S10C1
S09C1
S08C1 xxxx xxxx 63, 187
LCDDATA6
LCDDATA5⁽²⁾
S07C1
S47C0
S06C1
S46C0
S05C1
S45C0
S04C1
S44C0
S03C1
S43C0
S02C1
S42C0
S01C1
S41C0
S00C1
S40C0
xxxx xxxx 63, 187
xxxx xxxx 63, 187
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 63, 174
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 63, 174
CCP1CON
—
—
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 63, 173
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 63, 174
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 64, 174
CCP2CON
—
—
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 64, 173
SPBRG2
AUSART Baud Rate Generator Register
0000 0000 64, 278
RCREG2
AUSART Receive Register
0000 0000 64, 283
TXREG2
AUSART Transmit Register
0000 0000 64, 281
TXSTA2
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 64, 276
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 64, 277
RTCCFG
RTCEN
—
RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0-00 0000 64, 157
RTCCAL
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0 0000 0000 64, 158
RTCVALH
RTCC Value High Register Window based on RTCPTR<1:0>
xxxx xxxx 64, 160
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode. See Section 18.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
 2010 Microchip Technology Inc.
DS39933D-page 79