PIC18F87J90 Datasheet, PDF (129/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
TABLE 10-12: PORTE FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/LCDBIAS1
RE0
0
O
DIG LATE<0> data output.
1
I
ST PORTE<0> data input.
LCDBIAS1
—
I
ANA LCD module bias voltage input.
RE1/LCDBIAS2
RE1
0
O
DIG LATE<1> data output.
1
I
ST PORTE<1> data input.
LCDBIAS2
—
I
ANA LCD module bias voltage input.
RE3/COM0
RE3
0
O
DIG LATE<3> data output.
1
I
ST PORTE<3> data input.
COM0
x
O
ANA LCD Common 0 output; disables all other outputs.
RE4/COM1
RE4
0
O
DIG LATE<4> data output.
1
I
ST PORTE<4> data input.
COM1
x
O
ANA LCD Common 1 output; disables all other outputs.
RE5/COM2
RE5
0
O
DIG LATE<5> data output.
1
I
ST PORTE<5> data input.
COM2
x
O
ANA LCD Common 2 output; disables all other outputs.
RE6/COM3
RE6
0
O
DIG LATE<6> data output.
1
I
ST PORTE<6> data input.
COM3
x
O
ANA LCD Common 3 output; disables all other outputs.
RE7/CCP2/
SEG31
RE7
CCP2⁽¹⁾
0
O
DIG LATE<7> data output.
1
I
ST PORTE<7> data input.
0
O
DIG CCP2 compare/PWM output; takes priority over port data.
1
I
ST CCP2 capture input.
SEG31
x
O
ANA Segment 31 analog output for LCD; disables digital output.
Legend:
Note 1:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTE
RE7
RE6
RE5
RE4
RE3
LATE
LATE7 LATE6 LATE5 LATE4 LATE3
TRISE
PORTG
TRISE7
RDPU
TRISE6
REPU
TRISE5
RJPU⁽¹⁾
TRISE4
RG4
TRISE3
RG3
TRISG
SPIOD CCP2OD CCP1OD TRISG4 TRISG3
LCDCON LCDEN SLPEN WERR
—
CS1
LCDSE3
SE31
SE30
SE29
SE28
SE27
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on PIC18F6XJ90 devices, read as ‘0’.
—
—
—
RG2
TRISG2
CS0
SE26
RE1
LATE1
TRISE1
RG1
TRISG1
LMUX1
SE25
Bit 0
RE0
LATE0
TRISE0
RG0
TRISG0
LMUX0
SE24
Reset
Values
on page
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 2010 Microchip Technology Inc.
DS39933D-page 129