PIC18F87J90 Datasheet, PDF (265/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
FIGURE 19-4:
Write to TXREG1
BRG Output
(Shift Clock)
TX1 (pin)
TX1IF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
1 TCY
bit 1
Word 1
Word 1
Transmit Shift Reg
bit 7/8 _{Stop bit}
FIGURE 19-5:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG1
BRG Output
(Shift Clock)
TX1 (pin)
TX1IF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
1 TCY
Start bit
Word 1
Transmit Shift Reg.
bit 0
1 TCY
Note: This timing diagram shows two consecutive transmissions.
bit 1
Word 1
bit 7/8 Stop bit
Start bit
bit 0
Word 2
Word 2
Transmit Shift Reg.
TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
59
PIR1
—
ADIF
RC1IF TX1IF SSPIF
—
TMR2IF TMR1IF
62
PIE1
—
ADIE
RC1IE TX1IE SSPIE
—
TMR2IE TMR1IE 62
IPR1
—
ADIP
RC1IP TX1IP SSPIP
—
TMR2IP TMR1IP 62
RCSTA1
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
61
TXREG1 EUSART Transmit Register
61
TXSTA1
CSRC
TX9
TXEN
SYNC SENDB BRGH TRMT
TX9D
61
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
63
SPBRGH1 EUSART Baud Rate Generator Register High Byte
63
SPBRG1 EUSART Baud Rate Generator Register Low Byte
61
LATG
U2OD U1OD
—
LATG4 LATG3 LATG2 LATG1 LATG0
62
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
 2010 Microchip Technology Inc.
DS39933D-page 265