PIC18F87J90 Datasheet, PDF (78/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
TABLE 6-3: PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page
SPBRG1
EUSART Baud Rate Generator Low Byte
0000 0000 61, 259
RCREG1
EUSART Receive Register
0000 0000 61, 267
TXREG1
EUSART Transmit Register
0000 0000 61, 265
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 61, 256
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 61, 257
LCDPS
WFT
BIASMD
LCDA
WA
LP3
LP2
LP1
LP0
0000 0000 61, 185
LCDSE0
SE07
SE06
SE05
SE04
SE03
SE02
SE01
SE00 0000 0000 61, 186
LCDCON
LCDEN
SLPEN
WERR
—
CS1
CS0
LMUX1
LMUX0 000- 0000 61, 184
EECON2
EEPROM Control Register 2 (not a physical register)
---- ---- 61, 90
EECON1
—
—
WPROG
FREE
WRERR
WREN
WR
—
--00 x00- 61, 90
IPR3
—
LCDIP
RC2IP
TX2IP
CTMUIP CCP2IP CCP1IP RTCCIP -111 1111 62, 114
PIR3
—
LCDIF
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
RTCCIF -000 0000 62, 108
PIE3
—
LCDIE
RC2IE
TX2IE
CTMUIE CCP2IE CCP1IE RTCCIE -000 0000 62, 111
IPR2
OSCFIP
CMIP
—
—
BCLIP
LVDIP
TMR3IP
—
11-- 111- 62, 113
PIR2
OSCFIF
CMIF
—
—
BCLIF
LVDIF
TMR3IF
—
00-- 000- 62, 107
PIE2
OSCFIE
CMIE
—
—
BCLIE
LVDIE
TMR3IE
—
00-- 000- 62, 110
IPR1
—
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP TMR1IP -111 1-11 62, 112
PIR1
—
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF -000 0-00 62, 106
PIE1
OSCTUNE
TRISJ⁽²⁾
—
INTSRC
TRISJ7
ADIE
PLLEN⁽⁴⁾
TRISJ6
RC1IE
TUN5
TRISJ5
TX1IE
TUN4
TRISJ4
SSPIE
TUN3
TRISJ3
—
TUN2
TRISJ2
TMR2IE
TUN1
TRISJ1
TMR1IE
TUN0
TRISJ0
-000 0-00
0000 0000
1111 1111
62, 109
37, 62
62, 138
TRISH⁽²⁾
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0 1111 1111 62, 136
TRISG
SPIOD
CCP2OD CCP1OD TRISG4
TRISG3
TRISG2
TRISG1
TRISG0 0001 1111 62, 134
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
1111 111- 62, 132
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
—
TRISE1
TRISE0 1111 1-11 62, 129
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0 1111 1111 62, 127
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0 1111 1111 62, 125
TRISB
TRISA
TRISB7
TRISA7⁽⁵⁾
TRISB6
TRISA6⁽⁵⁾
TRISB5
TRISA5
TRISB4
TRISA4
TRISB3
TRISA3
TRISB2
TRISA2
TRISB1
TRISA1
TRISB0
TRISA0
1111 1111 62, 122
1111 1111 62, 119
LATJ⁽²⁾
LATH⁽²⁾
LATJ7
LATH7
LATJ6
LATH6
LATJ5
LATH5
LATJ4
LATH4
LATJ3
LATH3
LATJ2
LATH2
LATJ1
LATH1
LATJ0
LATH0
xxxx xxxx 62, 138
xxxx xxxx 62, 136
LATG
U2OD
U1OD
—
LATG4
LATG3
LATG2
LATG1
LATG0 00-x xxxx 62, 134
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
—
xxxx xxx- 62, 132
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
—
LATE1
LATE0 xxxx x-xx 62, 129
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0 xxxx xxxx 62, 127
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 xxxx xxxx 62, 125
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0 xxxx xxxx 62, 122
LATA
LATA7⁽⁵⁾
LATA6⁽⁵⁾
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0 xxxx xxxx 62, 119
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode. See Section 18.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
DS39933D-page 78
 2010 Microchip Technology Inc.