PIC18F87J90 Datasheet, PDF (194/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

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17.7 LCD Frame Frequency
The rate at which the COM and SEG outputs change is
called the LCD frame frequency. Frame frequency is
set by the LP<3:0> bits (LCDPS<3:0>) and is also
affected by the Multiplex mode being used. The rela-
tionship between the Multiplex mode, LP bits setting
and frame rate is shown in Table 17-4 and Table 17-5.
TABLE 17-4: FRAME FREQUENCY
FORMULAS
Multiplex
Mode
Frame Frequency (Hz)
Static
1/2
1/3
1/4
Clock Source/(4 x 1 x (LP<3:0> + 1))
Clock Source/(2 x 2 x (LP<3:0> + 1))
Clock Source/(1 x 3 x (LP<3:0> + 1))
Clock Source/(1 x 4 x (LP<3:0> + 1))
TABLE 17-5:
APPROXIMATE FRAME
FREQUENCY (IN Hz) FOR LP
PRESCALER SETTINGS
Multiplex Mode
LP<3:0>
Static
1/2
1/3
1/4
1
125
125
167
125
2
83
83
111
83
3
62
62
83
62
4
50
50
67
50
5
42
42
56
42
6
36
36
48
36
7
31
31
42
31
17.8 LCD Waveform Generation
LCD waveform generation is based on the principle
that the net AC voltage across the dark pixel should be
maximized and the net AC voltage across the clear
pixel should be minimized. The net DC voltage across
any pixel should be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data. The
pixel signal (COM-SEG) will have no DC component
and it can take only one of the two rms values. The
higher rms value will create a dark pixel and a lower
rms value will create a clear pixel.
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In the Type-A waveform, the
phase changes within each common type, whereas in
the Type-B waveform, the phase changes on each
frame boundary. Thus, the Type-A waveform maintains
0 VDC over a single frame, whereas the Type-B
waveform takes two frames.
Note 1: If the power-managed Sleep mode is
invoked while the LCD Sleep bit (SLPEN)
is set (LCDCON<6> is ‘1’), take care to
execute Sleep only when the VDC on all
the pixels is ‘0’.
2: When the LCD clock source is the system
clock, the LCD module will go to Sleep if
the microcontroller goes into Sleep mode,
regardless of the setting of the SLPEN bit.
Thus, always take care to see that the VDC
on all pixels is ‘0’ whenever Sleep mode is
invoked.
Figure 17-6 through Figure 17-16 provide waveforms
for static, half multiplex, one-third multiplex and quarter
multiplex drives for Type-A and Type-B waveforms.
DS39933D-page 194
 2010 Microchip Technology Inc.