PIC18F87J90 Datasheet, PDF (267/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
FIGURE 19-7:
RX1 (pin)
Rcv Shift Reg
Rcv Buffer Reg
RCREG1
Read Rcv
Buffer Reg
RC1IF
(Interrupt Flag)
OERR bit
CREN bit
ASYNCHRONOUS RECEPTION
Start
bit _{bit 0 bit 1}
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREG1
Start
bit 7/8 Stop bit
bit
Word 2
RCREG1
bit 7/8 Stop
bit
Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
—
ADIF
RC1IF TX1IF SSPIF
—
TMR2IF TMR1IF
62
PIE1
—
ADIE
RC1IE TX1IE SSPIE
—
TMR2IE TMR1IE
62
IPR1
—
ADIP
RC1IP TX1IP SSPIP
—
TMR2IP TMR1IP
62
RCSTA1
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
61
RCREG1 EUSART Receive Register
61
TXSTA1
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
61
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
63
SPBRGH1 EUSART Baud Rate Generator Register High Byte
61
SPBRG1 EUSART Baud Rate Generator Register Low Byte
61
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
 2010 Microchip Technology Inc.
DS39933D-page 267