PIC18F87J90 Datasheet, PDF (150/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
13.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
T2OUTPS<3:0>
T2CKPS<1:0>
FOSC/4
4
2
1:1, 1:4, 1:16
Prescaler
Internal Data Bus
Reset
TMR2
8
13.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 18.0
“Master Synchronous Serial Port (MSSP) Module”.
1:1 to 1:16
Postscaler
TMR2/PR2
Match
Comparator
8
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
PR2
8
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
59
PIR1
—
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF TMR1IF
62
PIE1
—
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE TMR1IE
62
IPR1
—
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP TMR1IP
62
TMR2 Timer2 Register
60
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 60
PR2 Timer2 Period Register
60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
DS39933D-page 150
 2010 Microchip Technology Inc.