PIC18F87J90 Datasheet, PDF (333/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
25.3 On-Chip Voltage Regulator
All of the PIC18F87J90 family devices power their core
digital logic at a nominal 2.5V. For designs that are
required to operate at a higher typical voltage, such as
3.3V, all devices in the PIC18F87J90 family incorporate
an on-chip regulator that allows the device to run its
core logic from VDD.
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn, pro-
vides power to the core from the other VDD pins. When
the regulator is enabled, a low-ESR filter capacitor
must be connected to the VDDCORE/VCAP pin
(Figure 25-2). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section 28.3 “DC Characteristics:
PIC18F87J90 Family (Industrial)”.
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 25-2 for possible
configurations.
25.3.1
VOLTAGE REGULATION AND
LOW-VOLTAGE DETECTION
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic. The regulator can provide this level from a VDD of
about 2.5V, all the way up to the device’s VDDMAX. It
does not have the capability to boost VDD levels below
2.5V.
In order to prevent “brown-out” conditions when the
voltage drops too low for the regulator, the regulator
enters Tracking mode. In Tracking mode, the regulator
output follows VDD with a typical voltage drop of
100 mV.
The on-chip regulator includes a simple Low-Voltage
Detect (LVD) circuit. If VDD drops too low to maintain
approximately 2.45V on VDDCORE, the circuit sets the
Low-Voltage Detect Interrupt Flag, LVDIF (PIR2<2>),
and clears the REGSLP (WDTCON<7>) bit, if it was
set.
This can be used to generate an interrupt and put the
application into a low-power operational mode, or trig-
ger an orderly shutdown. Low-Voltage Detection is only
available when the regulator is enabled.
FIGURE 25-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD):
3.3V
PIC18F87J90
VDD
ENVREG
VDDCORE/VCAP
CF
VSS
Regulator Disabled (ENVREG tied to ground):
2.5V⁽¹⁾
3.3V⁽¹⁾
PIC18F87J90
VDD
ENVREG
VDDCORE/VCAP
VSS
Regulator Disabled (VDD tied to VDDCORE):
2.5V⁽¹⁾
PIC18F87J90
VDD
ENVREG
VDDCORE/VCAP
VSS
Note 1:
These are typical operating voltages. For the
full operating ranges of VDD and VDDCORE,
refer to Section 28.1 “DC Characteristics:
Supply Voltage PIC18F87J90 Family
(Industrial)”.
 2010 Microchip Technology Inc.
DS39933D-page 333