PIC18F87J90 Datasheet, PDF (284/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
20.4 AUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA2<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA2<4>). In addition, enable bit, SPEN
(RCSTA2<7>), is set in order to configure the TX2 and
RX2 pins to CK2 (clock) and DT2 (data) lines,
respectively.
The Master mode indicates that the processor transmits
the master clock on the CK2 line.
20.4.1
AUSART SYNCHRONOUS MASTER
TRANSMISSION
The AUSART transmitter block diagram is shown in
Figure 20-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer Register,
TXREG2. The TXREG2 register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG2 (if available).
Once the TXREG2 register transfers the data to the
TSR register (occurs in one TCYCLE), the TXREG2 is
empty and the TX2IF flag bit (PIR3<4>) is set. The
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is
set regardless of the state of enable bit, TX2IE; it
cannot be cleared in software. It will reset only when
new data is loaded into the TXREG2 register.
While flag bit, TX2IF, indicates the status of the TXREG2
register, another bit, TRMT (TXSTA2<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRG2 register for the appropriate
baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREG2 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RX2/DT2 pin
TX2/CK2 pin
bit 0
bit 1
bit 2
Word 1
Write to
TXREG2 Reg
TX2IF bit
(Interrupt Flag)
TRMT bit
Write Word 1
Write Word 2
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 7
bit 0
bit 1
bit 7
Word 2
TXEN bit
‘1’
‘1’
Note: Sync Master mode, SPBRG2 = 0; continuous transmission of two 8-bit words.
DS39933D-page 284
 2010 Microchip Technology Inc.