PIC18F87J90 Datasheet, PDF (275/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
20.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The Addressable Universal Synchronous Asynchro-
nous Receiver Transmitter (AUSART) module is very
similar in function to the Enhanced USART module,
discussed in the previous chapter. It is provided as an
additional channel for serial communication with
external devices, for those situations that do not require
auto-baud detection or LIN/J2602 bus support.
The AUSART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The pins of the AUSART module are multiplexed with
the functions of PORTG (RG1/TX2/CK2 and
RG2/RX2/DT2/VLCAP1, respectively). In order to
configure these pins as an AUSART:
• bit, SPEN (RCSTA2<7>), must be set (= 1)
• bit, TRISG<2>, must be set (= 1)
• bit, TRISG<1>, must be cleared (= 0) for
Asynchronous and Synchronous Master modes
• bit, TRISG<1>, must be set (= 1) for Synchronous
Slave mode
Note:
The AUSART control will automatically
reconfigure the pin from input to output as
needed.
The driver for the TX2 output pin can also be optionally
configured as an open-drain output. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the U2OD
bit (LATG<7>). Setting the bit configures the pin for
open-drain operation.
20.1 Control Registers
The operation of the Addressable USART module is
controlled through two registers, TXSTA2 and
RXSTA2. These are detailed in Register 20-1 and
Register 20-2, respectively.
 2010 Microchip Technology Inc.
DS39933D-page 275