PIC18F87J90 Datasheet, PDF (118/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
TABLE 10-2: OUTPUT DRIVE LEVELS FOR
VARIOUS PORTS
Low
Medium
High
PORTA<5:0> PORTD
PORTA<7:6>
PORTF
PORTG
PORTH⁽¹⁾
PORTE
PORTJ⁽¹⁾
PORTB
PORTC
Note 1: Not available on PIC18F6XJ90 devices.
10.1.3 PULL-UP CONFIGURATION
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level
without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU and PJPU (PORTG<7:5>) for the other ports.
10.1.4 OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. This option is selectively enabled by
setting the open-drain control bit for the corresponding
module in TRISG and LATG. Their configuration is dis-
cussed in more detail in Section 10.4 “PORTC, TRISC
and LATC Registers”, Section 10.6 “PORTE, TRISE
and LATE Registers” and Section 10.8 “PORTG,
TRISG and LATG Registers”.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor,
provided by the user to a higher voltage level, up to 5V
(Figure 10-2). When a digital logic high signal is output,
it is pulled up to the higher voltage level.
FIGURE 10-2:
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
3.3V
+5V
PIC18F87J90
VDD
TXX ^3.3V
5V
(at logic ‘1’)
10.2 PORTA, TRISA and
LATA Registers
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISA and LATA.
RA4/T0CKI is a Schmitt Trigger input. All other PORTA
pins have TTL input levels and full CMOS output
drivers.
The RA4 pin is multiplexed with the Timer0 clock input
and one of the LCD segment drives. RA5 and RA<3:0>
are multiplexed with analog inputs for the A/D
Converter.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the PCFG<3:0>
control bits in the ADCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Note:
RA5 and RA<3:0> are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the exter-
nal (primary) oscillator circuit (HS Oscillator modes), or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use INTOSC or INTRC as the default oscillator mode
(FOSC2 Configuration bit is ‘0’), RA6 and RA7 are
automatically configured as digital I/O. The oscillator
and clock in/clock out functions are disabled.
RA1, RA4 and RA5 are multiplexed with LCD segment
drives, controlled by bits in the LCDSE1 and LCDSE2
registers. I/O port functionality is only available when
the LCD segments are disabled.
EXAMPLE 10-1: INITIALIZING PORTA
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTA
LATA
07h
ADCON1
0BFh
TRISA
; Initialize PORTA by
; clearing output latches
; Alternate method to
; clear output data latches
; Configure A/D
; for digital inputs
; Value used to initialize
; data direction
; Set RA<7, 5:0> as inputs,
; RA<6> as output
DS39933D-page 118
 2010 Microchip Technology Inc.