PIC18F87J90 Datasheet, PDF (76/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
TABLE 6-3: PIC18F87J90 FAMILY REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 59, 67
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 59, 67
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 59, 67
STKPTR
PCLATU
STKFUL
—
STKUNF
—
—
Return Stack Pointer
bit 21⁽¹⁾ Holding Register for PC<20:16>
uu-0 0000 59, 68
---0 0000 59, 67
PCLATH
Holding Register for PC<15:8>
0000 0000 59, 67
PCL
PC Low Byte (PC<7:0>)
0000 0000 59, 67
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 59, 92
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 59, 92
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 59, 92
TABLAT
Program Memory Table Latch
0000 0000 59, 92
PRODH
Product Register High Byte
xxxx xxxx 59, 99
PRODL
Product Register Low Byte
xxxx xxxx 59, 99
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 59, 103
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
RBIP 1111 1111 59, 104
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF 1100 0000 59, 105
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
59, 83
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
59, 84
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
59, 84
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
59, 84
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
N/A
59, 84
value of FSR0 offset by W
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 59, 83
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 59, 83
WREG
Working Register
xxxx xxxx 59
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
59, 83
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
59, 84
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
59, 84
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
59, 84
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
N/A
59, 84
value of FSR1 offset by W
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 60, 83
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 60, 83
BSR
—
—
—
—
Bank Select Register
---- 0000 60, 72
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
60, 83
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
60, 84
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
60, 84
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
60, 84
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
N/A
60, 84
value of FSR2 offset by W
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 60, 83
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 60, 83
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 60, 81
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode. See Section 18.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
DS39933D-page 76
 2010 Microchip Technology Inc.