PIC18F87J90 Datasheet, PDF (444/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
Bus Collision During a Repeated Start
Condition (Case 2) ............................................ 252
Bus Collision During a Start
Condition (SCL = 0) .......................................... 251
Bus Collision During a Stop
Condition (Case 1) ............................................ 253
Bus Collision During a Stop Condition (Case 2) ....... 253
Bus Collision During Start
Condition (SDA Only)........................................ 250
Bus Collision for Transmit and Acknowledge............ 249
Capture/Compare/PWM............................................ 415
CLKO and I/O ........................................................... 412
Clock Synchronization .............................................. 235
Clock/Instruction Cycle ............................................... 70
EUSART/AUSART Synchronous Receive
(Master/Slave)................................................... 424
EUSART/AUSART Synchronous Transmission
(Master/Slave)................................................... 424
Example SPI Master Mode (CKE = 0) ...................... 416
Example SPI Master Mode (CKE = 1) ...................... 417
Example SPI Slave Mode (CKE = 0) ........................ 418
Example SPI Slave Mode (CKE = 1) ........................ 419
External Clock ........................................................... 410
Fail-Safe Clock Monitor............................................. 336
First Start Bit Timing ................................................. 243
I²C Bus Data ............................................................. 421
I²C Bus Start/Stop Bits.............................................. 420
I²C Master Mode (7 or 10-Bit Transmission) ............ 246
I²C Master Mode (7-Bit Reception) ........................... 247
I²C Slave Mode (10-Bit Reception,
SEN = 0, ADMSK = 01001) .............................. 232
I²C Slave Mode (10-Bit Reception, SEN = 0) ........... 231
I²C Slave Mode (10-Bit Reception, SEN = 1) ........... 237
I²C Slave Mode (10-Bit Transmission)...................... 233
I²C Slave Mode (7-Bit Reception,
SEN = 0, ADMSK = 01011) .............................. 229
I²C Slave Mode (7-Bit Reception, SEN = 0) ............. 228
I²C Slave Mode (7-Bit Reception, SEN = 1) ............. 236
I²C Slave Mode (7-Bit Transmission)........................ 230
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode)......... 238
I²C Stop Condition Receive or Transmit Mode ......... 248
LCD Interrupt in Quarter Duty Cycle Drive................ 206
LCD Sleep Entry/Exit When SLPEN = 1
or CS1:CS0 = 00............................................... 207
MSSP I²C Bus Data .................................................. 422
MSSP I²C Bus Start/Stop Bits .................................. 422
PWM Output ............................................................. 179
Repeated Start Condition.......................................... 244
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ...... 413
Send Break Character Sequence ............................. 269
Slave Synchronization .............................................. 217
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................. 57
SPI Mode (Master Mode) .......................................... 216
SPI Mode (Slave Mode, CKE = 0) ............................ 218
SPI Mode (Slave Mode, CKE = 1) ............................ 218
Synchronous Reception (Master Mode,
SREN)....................................................... 272, 286
Synchronous Transmission............................... 270, 284
Synchronous Transmission
(Through TXEN)........................................ 271, 285
Time-out Sequence on Power-up (MCLR Not
Tied to VDD), Case 1 .......................................... 56
Time-out Sequence on Power-up (MCLR Not
Tied to VDD), Case 2 .......................................... 57
Time-out Sequence on Power-up (MCLR
Tied to VDD, VDD Rise Tpwrt) ............................. 56
Timer Pulse Generation............................................ 170
Timer0 and Timer1 External Clock ........................... 414
Transition for Entry to Idle Mode................................. 50
Transition for Entry to SEC_RUN Mode ..................... 47
Transition for Entry to Sleep Mode ............................. 49
Transition for Two-Speed Start-up
(INTRC to HSPLL)............................................ 334
Transition for Wake From Idle to Run Mode............... 50
Transition for Wake From Sleep (HSPLL) .................. 49
Transition From RC_RUN Mode to
PRI_RUN Mode.................................................. 48
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ................................... 47
Transition to RC_RUN Mode ...................................... 48
Type-A in 1/2 MUX, 1/2 Bias Drive ........................... 196
Type-A in 1/2 MUX, 1/3 Bias Drive ........................... 198
Type-A in 1/3 MUX, 1/2 Bias Drive ........................... 200
Type-A in 1/3 MUX, 1/3 Bias Drive ........................... 202
Type-A in 1/4 MUX, 1/3 Bias Drive ........................... 204
Type-A/Type-B in Static Drive .................................. 195
Type-B in 1/2 MUX, 1/2 Bias Drive ........................... 197
Type-B in 1/2 MUX, 1/3 Bias Drive ........................... 199
Type-B in 1/3 MUX, 1/2 Bias Drive ........................... 201
Type-B in 1/3 MUX, 1/3 Bias Drive ........................... 203
Type-B in 1/4 MUX, 1/3 Bias Drive ........................... 205
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements .................... 415
CLKO and I/O Requirements.................................... 412
EUSART/AUSART Synchronous Receive
Requirements ................................................... 424
EUSART/AUSART Synchronous Transmission
Requirements ................................................... 424
Example SPI Mode Requirements (Master Mode,
CKE = 0) ........................................................... 416
Example SPI Mode Requirements (Master Mode,
CKE = 1) ........................................................... 417
Example SPI Mode Requirements (Slave Mode,
CKE = 0) ........................................................... 418
Example SPI Slave Mode Requirements
(CKE = 1).......................................................... 419
External Clock Requirements ................................... 410
I²C Bus Data Requirements (Slave Mode) ............... 421
I²C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 420
Internal RC Accuracy (INTOSC and INTRC)............ 411
MSSP I²C Bus Data Requirements .......................... 423
MSSP I²C Bus Start/Stop Bits Requirements........... 422
PLL Clock ................................................................. 411
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements......................................... 413
Timer0 and Timer1 External Clock
Requirements ................................................... 414
Top-of-Stack Access........................................................... 67
TSTFSZ ............................................................................ 379
Two-Speed Start-up.................................................. 325, 334
Two-Word Instructions
Example Cases........................................................... 71
DS39933D-page 444
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