PIC18F87J90 Datasheet, PDF (219/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
18.3.9
OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTRC source. See Section 3.3 “Clock Sources
and Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set,
and if enabled, will wake the device.
18.3.10 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
18.3.11 BUS MODE COMPATIBILITY
Table 18-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 18-1: SPI BUS MODES
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also an SMP bit which controls when the data
is sampled.
TABLE 18-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF
PIR1
—
ADIF
RC1IF TX1IF SSPIF
—
PIE1
—
ADIE
RC1IE TX1IE SSPIE
—
IPR1
—
ADIP
RC1IP TX1IP SSPIP
—
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2
TRISG
SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2
SSPBUF MSSP Receive Buffer/Transmit Register
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2
SSPSTAT
SMP
CKE
D/A
P
S
R/W
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Bit 1
INT0IF
TMR2IF
TMR2IE
TMR2IP
TRISC1
TRISF1
TRISG1
SSPM1
UA
Bit 0
RBIF
TMR1IF
TMR1IE
TMR1IP
TRISC0
—
TRISG0
SSPM0
BF
Reset
Values
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 2010 Microchip Technology Inc.
DS39933D-page 219