PIC18F87J90 Datasheet, PDF (168/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
TABLE 15-4: ALRMVAL REGISTER
MAPPING
Alarm Value Register Window
ALRMPTR<1:0>
ALRMVALH
ALRMVALL
00
ALRMMIN
ALRMSEC
01
ALRMWD
ALRMHR
10
ALRMMNTH
ALRMDAY
11
—
—
15.2.9 CALIBRATION
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than three
seconds per month.
To perform this calibration, find the number of error
clock pulses and store the value into the lower half of
the RTCCAL register. The 8-bit, signed value, loaded
into RTCCAL, is multiplied by 4 and will either be added
or subtracted from the RTCC timer, once every minute.
To calibrate the RTCC module:
1. Use another timer resource on the device to find
the error of the 32.768 kHz crystal.
2. Convert the number of error clock pulses per
minute (see Equation 15-1).
EQUATION 15-1: CONVERTING ERROR,
CLOCK PULSES
(Ideal Frequency (32,758) – Measured Frequency) * 60 =
Error Clocks per Minute
• If the oscillator is faster than ideal (negative result
from step 2), the RCFGCALL register value
needs to be negative. This causes the specified
number of clock pulses to be subtracted from the
timer counter once every minute.
• If the oscillator is slower than ideal (positive
result from step 2), the RCFGCALL register
value needs to be positive. This causes the
specified number of clock pulses to be added to
the timer counter once every minute.
3. Load the RTCCAL register with the correct value.
Writes to the RTCCAL register should occur only when
the timer is turned off or immediately after the rising
edge of the seconds pulse.
Note:
In determining the crystal’s error value, it
is the user’s responsibility to include the
crystal’s initial error from drift due to
temperature or crystal aging.
15.3 Alarm
The alarm features and characteristics are:
• Configurable from half a second to one year
• Enabled using the ALRMEN bit (ALRMCFG<7>,
Register 15-4)
• Offers one-time and repeat alarm options
15.3.1 CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. The bit will
not be cleared if the CHIME bit = 1 or if ALRMRPT  0.
The interval selection of the alarm is configured
through the ALRMCFG (AMASK<3:0>) bits (see
Figure 15-5). These bits determine which and how
many digits of the alarm must match the clock value for
the alarm to occur.
The alarm can also be configured to repeat based on a
preconfigured interval. The number of times this
occurs, after the alarm is enabled, is stored in the
ALRMRPT register.
Note:
While the alarm is enabled (ALRMEN = 1),
changing any of the registers, other than
the RTCCAL, ALRMCFG and ALRMRPT
registers and the CHIME bit, can result in
a false alarm event leading to a false
alarm interrupt. To avoid this, only change
the timer and alarm values while the alarm
is disabled (ALRMEN = 0). It is recom-
mended that the ALRMCFG and
ALRMRPT registers and CHIME bit be
changed when RTCSYNC = 0.
DS39933D-page 168
 2010 Microchip Technology Inc.