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| PIC18F87J90 Datasheet, PDF (77/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology | |||
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PIC18F87J90 FAMILY
TABLE 6-3: PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page
TMR0H
Timer0 Register High Byte
0000 0000 60, 141
TMR0L
Timer0 Register Low Byte
xxxx xxxx 60, 141
T0CON
TMR0ON T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0 1111 1111 60, 141
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0 0110 q000 36, 60
LCDREG
â
CPEN
BIAS2
BIAS1
BIAS0
MODE13 CKSEL1 CKSEL0 -011 1100 60, 189
WDTCON
REGSLP
â
â
â
â
â
â
SWDTEN 0--- ---0 60, 332
RCON
IPEN
â
CM
RI
TO
PD
POR
BOR 0-11 11q0 54, 60
TMR1H
Timer1 Register High Byte
xxxx xxxx 60, 147
TMR1L
Timer1 Register Low Byte
xxxx xxxx 60, 147
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 60, 143
TMR2
Timer2 Register
0000 0000 60, 150
PR2
Timer2 Period Register
1111 1111 60, 150
T2CON
â
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 60, 149
SSPBUF
SSPADD
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I2C⢠Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode.
xxxx xxxx
0000 0000
60, 219,
254
60, 254
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 60, 212,
221
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 60, 213,
222
SSPCON2
GCEN
GCEN
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3)
SEN
SEN
0000 0000 60, 223,
224
ADRESH
A/D Result Register High Byte
xxxx xxxx 61, 297
ADRESL
A/D Result Register Low Byte
xxxx xxxx 61, 297
ADCON0
ADCAL
â
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON 0-00 0000 61, 289
ADCON1
TRIGSEL
â
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0 0-00 0000 61, 290
ADCON2
LCDDATA4
ADFM
S39C0(2)
â
S38C0(2)
ACQT2
S37C0(2)
ACQT1
S36C0(2)
ACQT0
S35C0(2)
ADCS2
S34C0(2)
ADCS1
S33C0(2)
ADCS0
S32C0
0-00 0000 61, 291
xxxx xxxx 61, 187
LCDDATA3
S31C0
S30C0
S29C0
S28C0
S27C0
S26C0
S25C0
S24C0 xxxx xxxx 61, 187
LCDDATA2
S23C0
S22C0
S21C0
S20C0
S19C0
S18C0
S17C0
S16C0 xxxx xxxx 61, 187
LCDDATA1
S15C0
S14C0
S13C0
S12C0
S11C0
S10C0
S09C0
S08C0 xxxx xxxx 61, 187
LCDDATA0
LCDSE5(2)
LCDSE4
S07C0
SE47
SE39(2)
S06C0
SE46
SE38(2)
S05C0
SE45
S37(2)
S04C0
SE44
SE36(2)
S03C0
SE43
SE35(2)
S02C0
SE42
SE34(2)
S01C0
SE41
SE33(2)
S00C0
SE40
SE32
xxxx xxxx
0000 0000
0000 0000
61, 187
61, 187
61, 187
LCDSE3
SE31
SE30
SE29
SE28
SE27
SE26
SE25
SE24 0000 0000 61, 187
LCDSE2
SE23
SE22
SE21
SE20
SE19
SE18
SE17
SE16 0000 0000 61, 187
LCDSE1
SE15
SE14
SE13
SE12
SE11
SE10
SE09
SE08 0000 0000 61, 187
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0 0000 0000 61, 305
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0 0000 0111 61, 299
TMR3H
Timer3 Register High Byte
xxxx xxxx 61, 153
TMR3L
Timer3 Register Low Byte
xxxx xxxx 61, 153
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 61, 151
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as â0â. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I2C⢠Slave mode. See Section 18.4.3.2 âAddress
Maskingâ for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as â0â. See Section 3.4.3 âPLL
Frequency Multiplierâ for details.
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as â0â.
ï£ 2010 Microchip Technology Inc.
DS39933D-page 77
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