PIC18F87J90 Datasheet, PDF (220/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
18.4 I²C Mode
The MSSP module in I²C mode fully implements all
master and slave functions (including general call
support), and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs by setting
the TRISC<4:3> bits.
FIGURE 18-7:
MSSP BLOCK DIAGRAM
(I²C™ MODE)
SCL
SDA
Read
Internal
Data Bus
Write
SSPBUF reg
Shift
Clock
SSPSR reg
MSb
LSb
Match Detect
Address Mask
Addr Match
SSPADD reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPSTAT reg)
18.4.1 REGISTERS
The MSSP module has six registers for I²C operation.
These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I²C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
Many of the bits in SSPCON2 assume different
functions, depending on whether the module is operat-
ing in Master or Slave mode. The SSPCON2<5:2> bits
also assume different names in Slave mode. The differ-
ent aspects of SSPCON2 are shown in Register 18-5
(for Master mode) and Register 18-6 (Slave mode).
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
The SSPADD register holds the slave device address
when the MSSP is configured in I²C Slave mode. When
the MSSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate Generator
reload value.
In receive operations, SSPSR and SSPBUF together,
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
DS39933D-page 220
 2010 Microchip Technology Inc.