PIC18F87J90 Datasheet, PDF(119/450 Page) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIC18F87J90 Datasheet, PDF (119/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

◁

PIC18F87J90 FAMILY

TABLE 10-3: PORTA FUNCTIONS

Pin Name

Function

TRIS

Setting

I/O

I/O

Type

Description

RA0/AN0

RA0

0

O

DIG LATA<0> data output; not affected by analog input.

1

I

TTL PORTA<0> data input; disabled when analog input enabled.

AN0

1

I

ANA A/D Input Channel 0. Default input configuration on POR; does not

affect digital output.

RA1/AN1/SEG18

RA1

0

O

DIG LATA<1> data output; not affected by analog input.

1

I

TTL PORTA<1> data input; disabled when analog input enabled.

AN1

1

I

ANA A/D Input Channel 1. Default input configuration on POR; does not

affect digital output.

SEG18

x

O ANA LCD Segment 18 output; disables all other pin functions.

RA2/AN2/VREF-

RA2

0

O

DIG LATA<2> data output; not affected by analog input.

1

I

TTL PORTA<2> data input; disabled when analog functions enabled.

AN2

1

I

ANA A/D Input Channel 2. Default input configuration on POR.

VREF-

1

I

ANA A/D and comparator low reference voltage input.

RA3/AN3/VREF+

RA3

0

O

DIG LATA<3> data output; not affected by analog input.

1

I

TTL PORTA<3> data input; disabled when analog input enabled.

AN3

1

I

ANA A/D Input Channel 3. Default input configuration on POR.

VREF+

1

I

ANA A/D and comparator high reference voltage input.

RA4/T0CKI/

SEG14

RA4

0

O

DIG LATA<4> data output.

1

I

ST PORTA<4> data input. Default configuration on POR.

T0CKI

x

I

ST Timer0 clock input.

SEG14

x

O ANA LCD Segment 14 output; disables all other pin functions.

RA5/AN4/SEG15

RA5

0

O

DIG LATA<5> data output; not affected by analog input.

1

I

TTL PORTA<5> data input; disabled when analog input enabled.

AN4

1

I

ANA A/D Input Channel 4. Default configuration on POR.

SEG15

x

O ANA LCD Segment 15 output; disables all other pin functions.

OSC2/CLKO/RA6

OSC2

x

O ANA Main oscillator feedback output connection (HS and HSPLL modes).

CLKO

x

O

DIG System cycle clock output (FOSC/4) (EC and ECPLL modes).

RA6

0

O

DIG LATA<6> data output; disabled when FOSC2 Configuration bit is set.

1

I

TTL PORTA<6> data input; disabled when FOSC2 Configuration bit is set.

OSC1/CLKI/RA7 OSC1

x

I

ANA Main oscillator input connection (HS and HSPLL modes).

CLKI

x

I

ANA Main external clock source input (EC and ECPLL modes).

RA7

0

O

DIG LATA<7> data output; disabled when FOSC2 Configuration bit is set.

1

I

TTL PORTA<7> data input; disabled when FOSC2 Configuration bit is set.

Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,

TTL = TTL Buffer Input, x = Donât care (TRIS bit does not affect port direction or is overridden for this option).

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Values

on page

PORTA

LATA

TRISA

ADCON1

LCDSE1

LCDSE2

Legend:

Note 1:

RA7(1)

RA6(1)

RA5

RA4

RA3

RA2

RA1

RA0

63

LATA7(1) LATA6(1)

LATA5

LATA4

LATA3

LATA2

LATA1

LATA0

62

TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

62

TRIGSEL

â

VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

61

SE15

SE14

SE13

SE12

SE11

SE10

SE09

SE08

61

SE23

SE22

SE21

SE20

SE19

SE18

SE17

SE16

61

â = unimplemented, read as â0â. Shaded cells are not used by PORTA.

These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are

disabled and read as âxâ.

ï£ 2010 Microchip Technology Inc.

DS39933D-page 119

▷