PIC18F87J90 Datasheet, PDF (288/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
20.5.2
AUSART SYNCHRONOUS
SLAVE RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep or any
Idle mode, and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep, or any Idle mode, then a word may be
received while in this Low-Power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG2 register; if the RC2IE enable bit is set, the
interrupt generated will wake the chip from Low-Power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RC2IE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
5. Flag bit, RC2IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC2IE, was set.
6. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG2 register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR3
—
LCDIF
RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF
62
PIE3
—
LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE
62
IPR3
—
LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP
62
RCSTA2
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
64
RCREG2 AUSART Receive Register
64
TXSTA2
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D
64
SPBRG2 AUSART Baud Rate Generator Register
64
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS39933D-page 288
 2010 Microchip Technology Inc.