PIC18F87J90 Datasheet, PDF (274/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
19.5.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode, and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this Low-Power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG1 register. If the RC1IE enable bit is set, the
interrupt generated will wake the chip from the
Low-Power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RC1IE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
5. Flag bit, RC1IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC1IE, was set.
6. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG1 register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
—
ADIF
RC1IF TX1IF SSPIF
—
TMR2IF TMR1IF
62
PIE1
—
ADIE
RC1IE TX1IE SSPIE
—
TMR2IE TMR1IE
62
IPR1
—
ADIP
RC1IP TX1IP SSPIP
—
TMR2IP TMR1IP
62
RCSTA1
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
61
RCREG1 EUSART Receive Register
61
TXSTA1
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
61
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
63
SPBRGH1 EUSART Baud Rate Generator Register High Byte
63
SPBRG1 EUSART Baud Rate Generator Register Low Byte
61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS39933D-page 274
 2010 Microchip Technology Inc.