PIC18F87J90 Datasheet, PDF (413/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
FIGURE 28-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
I/O pins
Note: Refer to Figure 28-3 for load conditions.
30
34
31
34
TABLE 28-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min Typ Max Units
Conditions
30
TMCL MCLR Pulse Width (low)
2 TCY
10
—
TCY
(Note 1)
31
TWDT Watchdog Timer Time-out Period
(no postscaler)
3.4
4.0
4.6
ms
32
TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC
TOSC = OSC1 period
33
TPWRT Power-up Timer Period
45.8 65.5 85.2
ms
34
TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
2
—
µs
38
TCSD CPU Start-up Time
—
10
—
µs
200
µs Voltage Regulator
enabled and put to
sleep
39
TIOBST Time for INTOSC to Stabilize
—
1
—
µs
Note 1: To ensure device Reset, MCLR must be low for at least 2 TCY or 400 s, whichever is lower.
 2010 Microchip Technology Inc.
DS39933D-page 413