PIC18F87J90 Datasheet, PDF (215/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
18.3.3 ENABLING SPI I/O
To enable the serial port, the MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISF<7> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
18.3.4 OPEN-DRAIN OUTPUT OPTION
The drivers for the SDO output and SCK clock pins can
be optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
to a higher level through an external pull-up resistor,
and allows the output to communicate with external
circuits without the need for additional level shifters.
The open-drain output option is controlled by the
SPIOD bit (TRISG<7>). Setting this bit configures both
pins for open-drain operation.
18.3.5 TYPICAL CONNECTION
Figure 18-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
FIGURE 18-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
SDO
Serial Input Buffer
(SSPBUF)
SPI Slave SSPM<3:0> = 010x
SDI
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb
LSb
PROCESSOR 1
SDI
SCK
Serial Clock
SDO
Shift Register
(SSPSR)
MSb
LSb
SCK
PROCESSOR 2
 2010 Microchip Technology Inc.
DS39933D-page 215