PIC18F87J90 Datasheet, PDF (167/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

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15.2.4 LEAP YEAR
Since the year range on the RTCC module is 2000 to
2099, the leap year calculation is determined by any year
divisible by 4 in the above range. Only February is
effected in a leap year.
February will have 29 days in a leap year and 28 days in
any other year.
15.2.5 GENERAL FUNCTIONALITY
All Timer registers containing a time value of seconds or
greater are writable. The user configures the time by
writing the required year, month, day, hour, minutes and
seconds to the Timer registers, via register pointers (see
Section 15.2.8 “Register Mapping”).
The timer uses the newly written values and proceeds
with the count from the required starting point.
The RTCC is enabled by setting the RTCEN bit
(RTCCFG<7>). If enabled while adjusting these regis-
ters, the timer still continues to increment. However, any
time the MINSEC register is written to, both of the timer
prescalers are reset to ‘0’. This allows fraction of a
second synchronization.
The Timer registers are updated in the same cycle as
the write instruction’s execution by the CPU. The user
must ensure that when RTCEN = 1, the updated
registers will not be incremented at the same time. This
can be accomplished in several ways:
• By checking the RTCSYNC bit (RTCCFG<4>)
• By checking the preceding digits from which a
carry can occur
• By updating the registers immediately following
the seconds pulse (or alarm interrupt)
The user has visibility to the half-second field of the
counter. This value is read-only and can be reset only
by writing to the lower half of the SECONDS register.
15.2.6
SAFETY WINDOW FOR REGISTER
READS AND WRITES
The RTCSYNC bit indicates a time window during
which the RTCC clock domain registers can be safely
read and written without concern about a rollover.
When RTCSYNC = 0, the registers can be safely
accessed by the CPU.
Whether RTCSYNC = 1 or 0, the user should employ a
firmware solution to ensure that the data read did not
fall on a rollover boundary, resulting in an invalid or
partial read. This firmware solution would consist of
reading each register twice and then comparing the two
values. If the two values matched, then a rollover did
not occur.
15.2.7 WRITE LOCK
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RTCCFG<5>) must be set.
To avoid accidental writes to the RTCC Timer register,
it is recommended that the RTCWREN bit
(RTCCFG<5>) be kept clear at any time other than
while writing to it. For the RTCWREN bit to be set, there
is only one instruction cycle time window allowed
between the 55h/AA sequence and the setting of
RTCWREN. For that reason, it is recommended that
users follow the code example in Example 15-1.
EXAMPLE 15-1: SETTING THE RTCWREN
BIT
movlw
movwf
movlw
movwf
bsf
0x55
EECON2
0xAA
EECON2
RTCCFG,RTCWREN
15.2.8 REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Timer registers are accessed through
corresponding register pointers. The RTCC Value
register window (RTCVALH and RTCVALL) uses the
RTCPTR bits (RTCCFG<1:0>) to select the required
Timer register pair.
By reading or writing to the RTCVALH register, the
RTCC Pointer value (RTCPTR<1:0>) decrements by ‘1’
until it reaches ‘00’. Once it reaches ‘00’, the MINUTES
and SECONDS value will be accessible through
RTCVALH and RTCVALL until the pointer value is
manually changed.
TABLE 15-3: RTCVALH AND RTCVALL
REGISTER MAPPING
RTCPTR<1:0>
RTCC Value Register Window
RTCVALH
RTCVALL
00
MINUTES
SECONDS
01
WEEKDAY
HOURS
10
MONTH
DAY
11
—
YEAR
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits (ALRMCFG<1:0>)
to select the desired Alarm register pair.
By reading or writing to the ALRMVALH register, the
Alarm Pointer value, ALRMPTR<1:0>, decrements by ‘1’
until it reaches ‘00’. Once it reaches ‘00’, the ALRMMIN
and ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
 2010 Microchip Technology Inc.
DS39933D-page 167