PIC18F87J90 Datasheet, PDF (189/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
17.3 LCD Bias Generation
The LCD driver module is capable of generating the
required bias voltages for LCD operation with a mini-
mum of external components. This includes the ability
to generate the different voltage levels required by the
different bias types that are required by the LCD. The
driver module can also provide bias voltages, both
above and below microcontroller VDD, through the use
of an on-chip LCD voltage regulator.
17.3.1 LCD BIAS TYPES
PIC18F87J90 family devices support three bias types
based on the waveforms generated to control
segments and commons:
• Static (two discrete levels)
• 1/2 Bias (three discrete levels
• 1/3 Bias (four discrete levels)
The use of different waveforms in driving the LCD is dis-
cussed in more detail in Section 17.8 “LCD Waveform
Generation”.
17.3.2 LCD VOLTAGE REGULATOR
The purpose of the LCD regulator is to provide proper
bias voltage and good contrast for the LCD, regardless
of VDD levels. This module contains a charge pump and
internal voltage reference. The regulator can be config-
ured by using external components to boost bias
voltage above VDD. It can also operate a display at a
constant voltage below VDD. The regulator can also be
selectively disabled to allow bias voltages to be
generated by an external resistor network.
The LCD regulator is controlled through the LCDREG
register (Register 17-5). It is enabled or disabled using
the CKSEL<1:0> bits, while the charge pump can be
selectively enabled using the CPEN bit. When the reg-
ulator is enabled, the MODE13 bit is used to select the
bias type. The peak LCD bias voltage, measured as a
difference between the potentials of LCDBIAS3 and
LCDBIAS0, is configured with the BIAS bits.
REGISTER 17-5: LCDREG: VOLTAGE REGULATOR CONTROL REGISTER
U-0
—
bit 7
RW-0
CPEN
RW-1
BIAS2
RW-1
BIAS1
RW-1
BIAS0
RW-1
MODE13
RW-0
CKSEL1
RW-0
CKSEL0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
CPEN: LCD Charge Pump Enable bit
1 = Charge pump enabled; highest LCD bias voltage is 3.6V
0 = Charge pump disabled; highest LCD bias voltage is AVDD
BIAS<2:0>: Regulator Voltage Output Control bits
111 = 3.60V peak (offset on LCDBIAS0 of 0V)
110 = 3.47V peak (offset on LCDBIAS0 of 0.13V)
101 = 3.34V peak (offset on LCDBIAS0 of 0.26V)
100 = 3.21V peak (offset on LCDBIAS0 of 0.39V)
011 = 3.08V peak (offset on LCDBIAS0 of 0.52V)
010 = 2.95V peak (offset on LCDBIAS0 of 0.65V)
001 = 2.82V peak (offset on LCDBIAS0 of 0.78V)
000 = 2.69V peak (offset on LCDBIAS0 of 0.91V)
MODE13: 1/3 LCD Bias Enable bit
1 = Regulator output supports 1/3 LCD Bias mode
0 = Regulator output supports static LCD Bias mode
CKSEL<1:0>: Regulator Clock Source Select bits
11 = INTRC
10 = INTOSC 8 MHz source
01 = Timer1 oscillator
00 = LCD regulator disabled
 2010 Microchip Technology Inc.
DS39933D-page 189