PIC18F87J90 Datasheet, PDF (184/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
17.1 LCD Registers
The LCD driver module has 33 registers:
• LCD Control Register (LCDCON)
• LCD Phase Register (LCDPS)
• LCDREG Register (LCD Regulator Control)
• Six LCD Segment Enable Registers
(LCDSE5:LCDSE0)
• 24 LCD Data Registers
(LCDDATA23:LCDDATA0)
17.1.1 LCD CONTROL REGISTERS
The LCDCON register, shown in Register 17-1,
controls the overall operation of the module. Once the
module is configured, the LCDEN (LCDCON<7>) bit is
used to enable or disable the LCD module. The LCD
panel can also operate during Sleep by clearing the
SLPEN (LCDCON<6>) bit.
The LCDPS register, shown in Register 17-2,
configures the LCD clock source prescaler and the type
of waveform: Type-A or Type-B. Details on these
features are provided in Section 17.2 “LCD Clock
Source”, Section 17.3 “LCD Bias Generation” and
Section 17.8 “LCD Waveform Generation”.
The LCDREG register is described in Section 17.3
“LCD Bias Generation”.
The LCD Segment Enable registers (LCDSEx)
configure the functions of the port pins. Setting the
segment enable bit for a particular segment configures
that pin as an LCD driver. The prototype LCDSE register
is shown in Register 17-3. There are six LCDSE
registers (LCDSE5:LCDSE0) listed in Table 17-1.
REGISTER 17-1: LCDCON: LCD CONTROL REGISTER
R/W-0
R/W-0
R/C-0
U-0
R/W-0
LCDEN
SLPEN
WERR
—
CS1
bit 7
R/W-0
CS0
R/W-0
LMUX1
R/W-0
LMUX0
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
LCDEN: LCD Driver Enable bit
1 = LCD driver module is enabled
0 = LCD driver module is disabled
SLPEN: LCD Driver Enable in Sleep mode bit
1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode
WERR: LCD Write Failed Error bit
1 = LCDDATAx register written while LCDPS<4> = 0 (must be cleared in software)
0 = No LCD write error
Unimplemented: Read as ‘0’
CS<1:0>: Clock Source Select bits
1x = INTRC (31 kHz)
01 = T13CKI (Timer1)
00 = System clock (FOSC/4)
LMUX<1:0>: Commons Select bits
LMUX<1:0>
Multiplex Type
Maximum Number of Pixels:
PIC18F6XJ90 PIC18F8XJ90
Bias Type
00
Static (COM0)
33
48
01
1/2 (COM1:COM0)
66
96
10
1/3 (COM2:COM0)
99
144
11
1/4 (COM3:COM0)
132
192
Static
1/2 or 1/3
1/2 or 1/3
1/3
DS39933D-page 184
 2010 Microchip Technology Inc.