PIC18F87J90 Datasheet, PDF (128/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
10.6 PORTE, TRISE and
LATE Registers
PORTE is a 7-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISE and LATE. All pins on PORTE are digital only
and tolerate voltages up to 5.5V.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output. The RE7 pin is also
configurable for open-drain output when CCP2 is active
on this pin. Open-drain configuration is selected by
setting the CCP2OD control bit (TRISG<6>)
Note: These pins are configured as digital inputs
on any device Reset.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PORTG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
Pins, RE<6:3>, are multiplexed with the LCD common
drives. I/O port functions are only available on those
PORTE pins depending on which commons are active.
The configuration is determined by the LMUX<1:0>
control bits (LCDCON<1:0>). The availability is
summarized in Table 10-11.
TABLE 10-11: PORTE PINS AVAILABLE IN
DIFFERENT LCD DRIVE
CONFIGURATIONS
LCDCON
<1:0>
Active LCD
Commons
PORTE Available
for I/O
00
COM0
RE6, RE5, RE4
01
COM0, COM1
RE6, RE5
10
COM0, COM1
RE6
and COM2
11
All (COM0
through COM3)
None
Pins, RE1 and RE0, are multiplexed with the functions
of LCDBIAS2 and LCDBIAS1. When LCD bias genera-
tion is required (i.e., any application where the device
is connected to an external LCD), these pins cannot be
used as digital I/O.
Note:
The pin corresponding to RE2 of other
PIC18F parts has the function of
LCDBIAS3 in this device. It cannot be used
as digital I/O.
RE7 is multiplexed with the LCD segment drive
(SEG31) controlled by the LCDSE3<7> bit. I/O port
function is only available when the segment is disabled.
RE7 can also be configured as the alternate peripheral
pin for the CCP2 module. This is done by clearing the
CCP2MX Configuration bit.
EXAMPLE 10-5: INITIALIZING PORTE
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
03h
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
DS39933D-page 128
 2010 Microchip Technology Inc.