PIC18F87J90 Datasheet, PDF (281/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
FIGURE 20-2:
Write to TXREG2
BRG Output
(Shift Clock)
TX2 (pin)
TX2IF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
1 TCY
bit 1
Word 1
Word 1
Transmit Shift Reg
bit 7/8 _{Stop bit}
FIGURE 20-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG2
BRG Output
(Shift Clock)
Word 1
Word 2
TX2 (pin)
TX2IF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Start bit
Word 1
Transmit Shift Reg.
bit 0
1 TCY
Note: This timing diagram shows two consecutive transmissions.
bit 1
Word 1
bit 7/8 Stop bit
Start bit
bit 0
Word 2
Word 2
Transmit Shift Reg.
TABLE 20-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
59
PIR3
—
LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 62
PIE3
—
LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 62
IPR3
—
LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 62
RCSTA2
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
64
TXREG2 AUSART Transmit Register
64
TXSTA2
CSRC
TX9
TXEN SYNC
—
BRGH TRMT
TX9D
64
SPBRG2 AUSART Baud Rate Generator Register
64
LATG
U2OD U1OD
—
LATG4 LATG3 LATG2 LATG1 LATG0
62
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
 2010 Microchip Technology Inc.
DS39933D-page 281