PIC18F87J90 Datasheet, PDF (438/450 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F87J90 FAMILY
F
Fail-Safe Clock Monitor............................................. 325, 335
Exiting Fail-Safe Operation ....................................... 336
Interrupts in Power-Managed Modes ........................ 336
POR or Wake-up From Sleep ................................... 336
WDT During Oscillator Failure .................................. 335
Fast Register Stack............................................................. 69
Firmware Instructions........................................................ 339
Flash Configuration Words................................................ 325
Flash Program Memory....................................................... 89
Associated Registers .................................................. 98
Control Registers ........................................................ 90
EECON1 and EECON2 ...................................... 90
TABLAT (Table Latch) Register.......................... 92
TBLPTR (Table Pointer) Register ....................... 92
Erase Sequence ......................................................... 94
Erasing ........................................................................ 94
Operation During Code-Protect .................................. 98
Reading....................................................................... 93
Table Pointer
Boundaries Based on Operation......................... 92
Table Pointer Boundaries ........................................... 92
Table Reads and Table Writes ................................... 89
Write Sequence .......................................................... 95
Write Sequence (Word Programming) ........................ 97
Writing ......................................................................... 95
Unexpected Termination..................................... 98
Write Verify ......................................................... 98
FSCM. See Fail-Safe Clock Monitor.
G
GOTO................................................................................ 360
H
Hardware Multiplier ............................................................. 99
8 x 8 Multiplication Algorithms .................................... 99
Operation .................................................................... 99
Performance Comparison (table) ................................ 99
I
I/O Ports ............................................................................ 117
Input Voltage Considerations .................................... 117
Open-Drain Outputs .................................................. 118
Output Pin Drive........................................................ 117
Pin Capabilities ......................................................... 117
Pull-up Configuration ................................................ 118
I²C Mode (MSSP) ............................................................. 220
Acknowledge Sequence Timing................................ 248
Associated Registers ................................................ 254
Baud Rate Generator ................................................ 241
Bus Collision
During a Repeated Start Condition ................... 252
During a Stop Condition.................................... 253
Clock Arbitration........................................................ 242
Clock Stretching ........................................................ 234
10-Bit Slave Receive Mode (SEN = 1).............. 234
10-Bit Slave Transmit Mode.............................. 234
7-Bit Slave Receive Mode (SEN = 1)................ 234
7-Bit Slave Transmit Mode................................ 234
Clock Synchronization and the CKP Bit .................... 235
Effects of a Reset...................................................... 249
General Call Address Support .................................. 238
I²C Clock Rate w/BRG .............................................. 241
Master Mode............................................................. 239
Baud Rate Generator ....................................... 241
Operation.......................................................... 240
Reception ......................................................... 245
Repeated Start Condition Timing ..................... 244
Start Condition Timing ...................................... 243
Transmission .................................................... 245
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 249
Multi-Master Mode .................................................... 249
Operation .................................................................. 225
Read/Write Bit Information (R/W Bit) ................ 225, 227
Registers .................................................................. 220
Serial Clock (SCK/SCL)............................................ 227
Slave Mode............................................................... 225
Address Masking .............................................. 226
Addressing........................................................ 225
Reception ......................................................... 227
Transmission .................................................... 227
Sleep Operation........................................................ 249
Stop Condition Timing .............................................. 248
INCF ................................................................................. 360
INCFSZ............................................................................. 361
In-Circuit Debugger........................................................... 337
In-Circuit Serial Programming (ICSP)....................... 325, 337
Indexed Literal Offset Addressing
and Standard PIC18 Instructions.............................. 386
Indexed Literal Offset Mode.............................................. 386
Indirect Addressing ............................................................. 83
INFSNZ............................................................................. 361
Initialization Conditions for all Registers ....................... 59–64
Instruction Cycle ................................................................. 70
Clocking Scheme........................................................ 70
Flow/Pipelining............................................................ 70
Instruction Set................................................................... 339
ADDLW..................................................................... 345
ADDWF..................................................................... 345
ADDWF (Indexed Literal Offset Mode) ..................... 387
ADDWFC .................................................................. 346
ANDLW..................................................................... 346
ANDWF..................................................................... 347
BC............................................................................. 347
BCF .......................................................................... 348
BN............................................................................. 348
BNC .......................................................................... 349
BNN .......................................................................... 349
BNOV ....................................................................... 350
BNZ .......................................................................... 350
BOV .......................................................................... 353
BRA .......................................................................... 351
BSF........................................................................... 351
BSF (Indexed Literal Offset Mode) ........................... 387
BTFSC ...................................................................... 352
BTFSS ...................................................................... 352
BTG .......................................................................... 353
BZ ............................................................................. 354
CALL......................................................................... 354
CLRF ........................................................................ 355
CLRWDT .................................................................. 355
COMF ....................................................................... 356
CPFSEQ ................................................................... 356
CPFSGT ................................................................... 357
CPFSLT .................................................................... 357
DS39933D-page 438
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