CD1284 Datasheet, PDF (84/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
At reset, all bits in the GPIO are cleared and the signals are programmed as inputs.
Note: Interrupts are not generated on signal changes within the General-Purpose I/O port; the CPU must
periodically poll GPIO to detect changes in external conditions. Therefore, if it is necessary to
detect changes, use the port with signals that change with low-duty cycles.
5.16
Parallel Port Interface
The CD1284 parallel port signals are implemented with Level 2 characteristics – as defined in the
IEEE STD 1284 specification with the exception of transient protection. The port can be directly
connected to the interface cable with the addition of a few external components. The components
consist of passive pull-up resistors, series-impedance-matching resistors, and clipping diodes.
Additional noise-filtering may be required in an end system. Figure 13 on page 85 shows a typical
interface with the components listed above.
Some system designs may require buffers between the CD1284 and the cable. Systems that require
drive cables longer than the specified maximum of 10 m or those that need to protect the CD1284
require inexpensive buffers between it and the cable. The device provides two signal outputs,
PDBEN and EBDIR, that can to connect and control buffers (such as, 74AS245 or equivalent).
These signals do not allow direct control of the buffer. However, the addition of an XNOR gate
provides both an enable control signal and a signal to select the direction of the buffer. PDBEN and
EBDIR are outputs from the control state machine that indicate its current state (see Figure 14 on
page 86).
84
Datasheet