CD1284 Datasheet, PDF (152/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Bit
Description
Mode Control: These three bits control the type of transfer desired and whether or not it is enabled to do so.
The ManMd bit selects Manual mode, which allows the user direct control over all parallel data and parallel
port control signals. MMDir controls the direction of the MDR (Manual Data register), and ManOE is the output
enable when MMDir = 1 (output mode).
E1284 allows the parallel port to engage in IEEE 1284 negotiations; ETxfr enables data transfers. The ETxfr
enable is only used for data transfers. EPP address read and write functions do not require that the ETxfr bit
be set.
7:5
ManMd
E1284
Etxfr
Mode
0
0
0
Compatibility mode; transfers disabled.
0
0
1
Compatibility mode; transfers enabled.
0
1
0
IEEE 1284 negotiation; transfers disabled.
0
1
1
IEEE 1284 negotiation; transfers enabled.
1
X
X
Manual mode.
Ig_SEL: This bit prevents the CD1284 from considering the state of the SLCTIN* input when deciding
whether or not to accept Compatibility mode forward data transfers.
4
When Ig_SEL is reset, SLCTIN* must be active (low) to receive data on the parallel port in response to a
STROBE* input. If Ig_SEL is set, SLCTIN* is not considered and data is accepted regardless of its state. The
Ig_SEL bit should be set/reset together with the E1284 bit.
Host Timer Test Control [1:0]: These two bits control the clock rate of the host timeout timer and are
3:2
intended primarily for manufacturing test purposes. As such, normal user-level programming should leave
these bits cleared (‘0’). When these bits are set to ‘1’, the timer is completely disabled – useful for factory
debug purposes.
Manual Mode Control: These two bits provide direction and output enable manual control over the parallel
port.
MMDir
ManOE
Mode
1:0
0
0
Reverse direction.
0
1
Reverse direction.
1
0
Forward direction disabled.
1
1
Forward direction enabled.
7.8.12
Special Command Register
Register Name: SCR
Register Description: Special Command
Access: R/W
Bit 7
Bit 6
Bit 5
0
0
0
Bit 4
TestMux
Bit 3
ClrPs
8-Bit Hex Address: 2A
Default Value: 00
Bit 2
SetPs
Bit 1
EPIrq
Bit 0
RevRq
This register provides the peripheral host processor to issue special commands to the channel
control state-machine. In response, the state-machine will perform the indicated IEEE STD 1284-
defined handshake on the parallel interface.
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Datasheet