CD1284 Datasheet, PDF (142/176 Pages) Intel Corporation – IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.7.10
The PFEP is cleared by a device or FIFO reset.
Parallel FIFO Fill Pointer Register
Register Name: PFFP
Register Description: Parallel FIFO Fill Pointer
Access: Read/Write
Bit 7
Bit 6
Bit 5
0
0
Bit 4
Bit 3
Bit 2
6-bit binary FIFO Pointer Value
8-Bit Hex Address: 38
Default Value: 00
Bit 1
Bit 0
This register holds the internal fill location pointer of the FIFO. It identifies the location in the
FIFO to receive the next data byte from the pipeline.
The PFFP is cleared by a device or FIFO reset.
7.7.11
Parallel FIFO Holding Register 1
Register Name: PFHR1
Register Description: Parallel FIFO Holding Register 1
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
8-bit Character Data
Bit 2
8-Bit Hex Address: 35
Default Value: 00
Bit 1
Bit 0
7.7.12
Parallel FIFO Holding Register 2
Register Name: PFHR2
Register Description: Parallel FIFO Holding Register 2
Access: Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
8-bit Character Data
Bit 2
8-Bit Hex Address: 36
Default Value: 00
Bit 1
Bit 0
These two 1-byte registers provide a data pipeline between the FIFO and DMA buffer. Data always
flows into PFHR1 first, then to PFHR2, and finally, either to the FIFO or the DMABUF register.
The flow is to the FIFO if DMAdir is ‘1’ and, from the FIFO if DMAdir is ‘0’. The pipeline and the
holding registers support ‘tagged’ data for complete support of ECP Parallel Port mode. Tagged
data is either an address or a run-length code.
If RLEen (PFCR[3]) is set, in the receive direction, run-length codes are captured in the RLCR for
decompression of received data. ECP address codes are recognized and pass into the PFHR1–
PFHR2 pipeline. The presence of an ECP address interrupts DMA flow and causes an interrupt to
the host so it can remove the tagged data from the pipeline by reading either PFHR2 or PFHR1.
In the transmit direction, the host can introduce ECP address (tagged) data or run-length codes for
precompressed data by setting the SetTAG bit (PFCR[2]) and writing the byte to be tagged to
PFHR1. For each tagged data transfer, the SetTAG bit must be set prior to writing to PFHR1. To
perform a tagged data transfer, the automatic DMA function must be disabled prior to the transfer
(set DMAen = 0). This can be done at the same time that SetTAG is set to ‘1’.
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Datasheet